1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 * Copyright (C) 2007 Kenati Technologies, Inc.
6 *
7 * board/sh7763rdp/lowlevel_init.S
8 */
9
10#include <config.h>
11
12#include <asm/processor.h>
13#include <asm/macro.h>
14
15	.global	lowlevel_init
16
17	.text
18	.align	2
19
20lowlevel_init:
21
22	write32	WDTCSR_A, WDTCSR_D	/* Watchdog Control / Status Register */
23
24	write32	WDTST_A, WDTST_D	/* Watchdog Stop Time Register */
25
26	write32	WDTBST_A, WDTBST_D	/*
27					 * 0xFFCC0008
28					 * Watchdog Base Stop Time Register
29					 */
30
31	write32	CCR_A, CCR_CACHE_ICI_D	/* Address of Cache Control Register */
32					/* Instruction Cache Invalidate */
33
34	write32	MMUCR_A, MMU_CONTROL_TI_D	/* MMU Control Register */
35						/* TI == TLB Invalidate bit */
36
37	write32	MSTPCR0_A, MSTPCR0_D	/* Address of Power Control Register 0 */
38
39	write32	MSTPCR1_A, MSTPCR1_D	/* Address of Power Control Register 1 */
40
41	write32	RAMCR_A, RAMCR_D
42
43	mov.l	MMSELR_A, r1
44	mov.l	MMSELR_D, r0
45	synco
46	mov.l	r0, @r1
47
48	mov.l	@r1, r2		/* execute two reads after setting MMSELR */
49	mov.l	@r1, r2
50	synco
51
52	/* issue memory read */
53	mov.l	DDRSD_START_A, r1	/* memory address to read*/
54	mov.l	@r1, r0
55	synco
56
57	write32	MIM8_A, MIM8_D
58
59	write32	MIMC_A, MIMC_D1
60
61	write32	STRC_A, STRC_D
62
63	write32	SDR4_A, SDR4_D
64
65	write32	MIMC_A, MIMC_D2
66
67	nop
68	nop
69	nop
70
71	write32	SCR4_A, SCR4_D3
72
73	write32	SCR4_A, SCR4_D2
74
75	write32	SDMR02000_A, SDMR02000_D
76
77	write32	SDMR00B08_A, SDMR00B08_D
78
79	write32	SCR4_A, SCR4_D2
80
81	write32	SCR4_A, SCR4_D4
82
83	nop
84	nop
85	nop
86	nop
87
88	write32	SCR4_A, SCR4_D4
89
90	nop
91	nop
92	nop
93	nop
94
95	write32	SDMR00308_A, SDMR00308_D
96
97	write32	MIMC_A, MIMC_D3
98
99	mov.l	SCR4_A, r1
100	mov.l	SCR4_D1, r0
101	mov.l	DELAY60_D, r3
102
103delay_loop_60:
104	mov.l	r0, @r1
105	dt	r3
106	bf	delay_loop_60
107	nop
108
109	write32	CCR_A, CCR_CACHE_D_2	/* Address of Cache Control Register */
110
111bsc_init:
112	write32	BCR_A, BCR_D
113
114	write32	CS0BCR_A, CS0BCR_D
115
116	write32	CS1BCR_A, CS1BCR_D
117
118	write32	CS2BCR_A, CS2BCR_D
119
120	write32	CS4BCR_A, CS4BCR_D
121
122	write32	CS5BCR_A, CS5BCR_D
123
124	write32	CS6BCR_A, CS6BCR_D
125
126	write32	CS0WCR_A, CS0WCR_D
127
128	write32	CS1WCR_A, CS1WCR_D
129
130	write32	CS2WCR_A, CS2WCR_D
131
132	write32	CS4WCR_A, CS4WCR_D
133
134	write32	CS5WCR_A, CS5WCR_D
135
136	write32	CS6WCR_A, CS6WCR_D
137
138	write32	CS5PCR_A, CS5PCR_D
139
140	write32	CS6PCR_A, CS6PCR_D
141
142	mov.l	DELAY200_D, r3
143
144delay_loop_200:
145	dt	r3
146	bf	delay_loop_200
147	nop
148
149	write16	PSEL0_A, PSEL0_D
150
151	write16	PSEL1_A, PSEL1_D
152
153	write32	ICR0_A, ICR0_D
154
155	stc sr, r0	/* BL bit off(init=ON) */
156	mov.l	SR_MASK_D, r1
157	and r1, r0
158	ldc r0, sr
159
160	rts
161	nop
162
163	.align	2
164
165DELAY60_D:	.long	60
166DELAY200_D:	.long	17800
167
168CCR_A:		.long	0xFF00001C
169MMUCR_A:	.long	0xFF000010
170RAMCR_A:	.long	0xFF000074
171
172/* Low power mode control */
173MSTPCR0_A:	.long	0xFFC80030
174MSTPCR1_A:	.long	0xFFC80038
175
176/* RWBT */
177WDTST_A:	.long	0xFFCC0000
178WDTCSR_A:	.long	0xFFCC0004
179WDTBST_A:	.long	0xFFCC0008
180
181/* BSC */
182MMSELR_A:	.long	0xFE600020
183BCR_A:		.long	0xFF801000
184CS0BCR_A:	.long	0xFF802000
185CS1BCR_A:	.long	0xFF802010
186CS2BCR_A:	.long	0xFF802020
187CS4BCR_A:	.long	0xFF802040
188CS5BCR_A:	.long	0xFF802050
189CS6BCR_A:	.long	0xFF802060
190CS0WCR_A:	.long	0xFF802008
191CS1WCR_A:	.long	0xFF802018
192CS2WCR_A:	.long	0xFF802028
193CS4WCR_A:	.long	0xFF802048
194CS5WCR_A:	.long	0xFF802058
195CS6WCR_A:	.long	0xFF802068
196CS5PCR_A:	.long	0xFF802070
197CS6PCR_A:	.long	0xFF802080
198DDRSD_START_A:	.long	0xAC000000
199
200/* INTC */
201ICR0_A:		.long	0xFFD00000
202
203/* DDR I/F */
204MIM8_A:		.long	0xFE800008
205MIMC_A:		.long	0xFE80000C
206SCR4_A:		.long	0xFE800014
207STRC_A:		.long	0xFE80001C
208SDR4_A:		.long	0xFE800034
209SDMR00308_A:	.long	0xFE900308
210SDMR00B08_A:	.long	0xFE900B08
211SDMR02000_A:	.long	0xFE902000
212
213/* GPIO */
214PSEL0_A:	.long	0xFFEF0070
215PSEL1_A:	.long	0xFFEF0072
216
217CCR_CACHE_ICI_D:.long	0x00000800
218CCR_CACHE_D_2:	.long	0x00000103
219MMU_CONTROL_TI_D:.long	0x00000004
220RAMCR_D:	.long	0x00000200
221MSTPCR0_D:	.long	0x00000000
222MSTPCR1_D:	.long	0x00000000
223
224MMSELR_D:	.long	0xa5a50000
225BCR_D:		.long	0x00000000
226CS0BCR_D:	.long	0x77777770
227CS1BCR_D:	.long	0x77777670
228CS2BCR_D:	.long	0x77777670
229CS4BCR_D:	.long	0x77777670
230CS5BCR_D:	.long	0x77777670
231CS6BCR_D:	.long	0x77777670
232CS0WCR_D:	.long	0x7777770F
233CS1WCR_D:	.long	0x22000002
234CS2WCR_D:	.long	0x7777770F
235CS4WCR_D:	.long	0x7777770F
236CS5WCR_D:	.long	0x7777770F
237CS6WCR_D:	.long	0x7777770F
238CS5PCR_D:	.long	0x77000000
239CS6PCR_D:	.long	0x77000000
240ICR0_D:		.long	0x00E00000
241MIM8_D:		.long	0x00000000
242MIMC_D1:	.long	0x01d10008
243MIMC_D2:	.long	0x01d10009
244MIMC_D3:	.long	0x01d10209
245SCR4_D1:	.long	0x00000001
246SCR4_D2:	.long	0x00000002
247SCR4_D3:	.long	0x00000003
248SCR4_D4:	.long	0x00000004
249STRC_D:		.long	0x000f3980
250SDR4_D:		.long	0x00000300
251SDMR00308_D:	.long	0x00000000
252SDMR00B08_D:	.long	0x00000000
253SDMR02000_D:	.long	0x00000000
254PSEL0_D:	.word	0x00000001
255PSEL1_D:	.word	0x00000244
256SR_MASK_D:	.long	0xEFFFFF0F
257WDTST_D:	.long	0x5A000FFF
258WDTCSR_D:	.long	0xA5000000
259WDTBST_D:	.long	0x55000000
260