1/*
2 * Copyright (C) 2008 Renesas Solutions Corp.
3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
4 * Copyright (C) 2007 Kenati Technologies, Inc.
5 *
6 * board/sh7763rdp/lowlevel_init.S
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include <version.h>
26
27#include <asm/processor.h>
28#include <asm/macro.h>
29
30	.global	lowlevel_init
31
32	.text
33	.align	2
34
35lowlevel_init:
36
37	write32	WDTCSR_A, WDTCSR_D	/* Watchdog Control / Status Register */
38
39	write32	WDTST_A, WDTST_D	/* Watchdog Stop Time Register */
40
41	write32	WDTBST_A, WDTBST_D	/*
42					 * 0xFFCC0008
43					 * Watchdog Base Stop Time Register
44					 */
45
46	write32	CCR_A, CCR_CACHE_ICI_D	/* Address of Cache Control Register */
47					/* Instruction Cache Invalidate */
48
49	write32	MMUCR_A, MMU_CONTROL_TI_D	/* MMU Control Register */
50						/* TI == TLB Invalidate bit */
51
52	write32	MSTPCR0_A, MSTPCR0_D	/* Address of Power Control Register 0 */
53
54	write32	MSTPCR1_A, MSTPCR1_D	/* Address of Power Control Register 1 */
55
56	write32	RAMCR_A, RAMCR_D
57
58	mov.l	MMSELR_A, r1
59	mov.l	MMSELR_D, r0
60	synco
61	mov.l	r0, @r1
62
63	mov.l	@r1, r2		/* execute two reads after setting MMSELR */
64	mov.l	@r1, r2
65	synco
66
67	/* issue memory read */
68	mov.l	DDRSD_START_A, r1	/* memory address to read*/
69	mov.l	@r1, r0
70	synco
71
72	write32	MIM8_A, MIM8_D
73
74	write32	MIMC_A, MIMC_D1
75
76	write32	STRC_A, STRC_D
77
78	write32	SDR4_A, SDR4_D
79
80	write32	MIMC_A, MIMC_D2
81
82	nop
83	nop
84	nop
85
86	write32	SCR4_A, SCR4_D3
87
88	write32	SCR4_A, SCR4_D2
89
90	write32	SDMR02000_A, SDMR02000_D
91
92	write32	SDMR00B08_A, SDMR00B08_D
93
94	write32	SCR4_A, SCR4_D2
95
96	write32	SCR4_A, SCR4_D4
97
98	nop
99	nop
100	nop
101	nop
102
103	write32	SCR4_A, SCR4_D4
104
105	nop
106	nop
107	nop
108	nop
109
110	write32	SDMR00308_A, SDMR00308_D
111
112	write32	MIMC_A, MIMC_D3
113
114	mov.l	SCR4_A, r1
115	mov.l	SCR4_D1, r0
116	mov.l	DELAY60_D, r3
117
118delay_loop_60:
119	mov.l	r0, @r1
120	dt	r3
121	bf	delay_loop_60
122	nop
123
124	write32	CCR_A, CCR_CACHE_D_2	/* Address of Cache Control Register */
125
126bsc_init:
127	write32	BCR_A, BCR_D
128
129	write32	CS0BCR_A, CS0BCR_D
130
131	write32	CS1BCR_A, CS1BCR_D
132
133	write32	CS2BCR_A, CS2BCR_D
134
135	write32	CS4BCR_A, CS4BCR_D
136
137	write32	CS5BCR_A, CS5BCR_D
138
139	write32	CS6BCR_A, CS6BCR_D
140
141	write32	CS0WCR_A, CS0WCR_D
142
143	write32	CS1WCR_A, CS1WCR_D
144
145	write32	CS2WCR_A, CS2WCR_D
146
147	write32	CS4WCR_A, CS4WCR_D
148
149	write32	CS5WCR_A, CS5WCR_D
150
151	write32	CS6WCR_A, CS6WCR_D
152
153	write32	CS5PCR_A, CS5PCR_D
154
155	write32	CS6PCR_A, CS6PCR_D
156
157	mov.l	DELAY200_D, r3
158
159delay_loop_200:
160	dt	r3
161	bf	delay_loop_200
162	nop
163
164	write16	PSEL0_A, PSEL0_D
165
166	write16	PSEL1_A, PSEL1_D
167
168	write32	ICR0_A, ICR0_D
169
170	stc sr, r0	/* BL bit off(init=ON) */
171	mov.l	SR_MASK_D, r1
172	and r1, r0
173	ldc r0, sr
174
175	rts
176	nop
177
178	.align	2
179
180DELAY60_D:	.long	60
181DELAY200_D:	.long	17800
182
183CCR_A:		.long	0xFF00001C
184MMUCR_A:	.long	0xFF000010
185RAMCR_A:	.long	0xFF000074
186
187/* Low power mode control */
188MSTPCR0_A:	.long	0xFFC80030
189MSTPCR1_A:	.long	0xFFC80038
190
191/* RWBT */
192WDTST_A:	.long	0xFFCC0000
193WDTCSR_A:	.long	0xFFCC0004
194WDTBST_A:	.long	0xFFCC0008
195
196/* BSC */
197MMSELR_A:	.long	0xFE600020
198BCR_A:		.long	0xFF801000
199CS0BCR_A:	.long	0xFF802000
200CS1BCR_A:	.long	0xFF802010
201CS2BCR_A:	.long	0xFF802020
202CS4BCR_A:	.long	0xFF802040
203CS5BCR_A:	.long	0xFF802050
204CS6BCR_A:	.long	0xFF802060
205CS0WCR_A:	.long	0xFF802008
206CS1WCR_A:	.long	0xFF802018
207CS2WCR_A:	.long	0xFF802028
208CS4WCR_A:	.long	0xFF802048
209CS5WCR_A:	.long	0xFF802058
210CS6WCR_A:	.long	0xFF802068
211CS5PCR_A:	.long	0xFF802070
212CS6PCR_A:	.long	0xFF802080
213DDRSD_START_A:	.long	0xAC000000
214
215/* INTC */
216ICR0_A:		.long	0xFFD00000
217
218/* DDR I/F */
219MIM8_A:		.long	0xFE800008
220MIMC_A:		.long	0xFE80000C
221SCR4_A:		.long	0xFE800014
222STRC_A:		.long	0xFE80001C
223SDR4_A:		.long	0xFE800034
224SDMR00308_A:	.long	0xFE900308
225SDMR00B08_A:	.long	0xFE900B08
226SDMR02000_A:	.long	0xFE902000
227
228/* GPIO */
229PSEL0_A:	.long	0xFFEF0070
230PSEL1_A:	.long	0xFFEF0072
231
232CCR_CACHE_ICI_D:.long	0x00000800
233CCR_CACHE_D_2:	.long	0x00000103
234MMU_CONTROL_TI_D:.long	0x00000004
235RAMCR_D:	.long	0x00000200
236MSTPCR0_D:	.long	0x00000000
237MSTPCR1_D:	.long	0x00000000
238
239MMSELR_D:	.long	0xa5a50000
240BCR_D:		.long	0x00000000
241CS0BCR_D:	.long	0x77777770
242CS1BCR_D:	.long	0x77777670
243CS2BCR_D:	.long	0x77777670
244CS4BCR_D:	.long	0x77777670
245CS5BCR_D:	.long	0x77777670
246CS6BCR_D:	.long	0x77777670
247CS0WCR_D:	.long	0x7777770F
248CS1WCR_D:	.long	0x22000002
249CS2WCR_D:	.long	0x7777770F
250CS4WCR_D:	.long	0x7777770F
251CS5WCR_D:	.long	0x7777770F
252CS6WCR_D:	.long	0x7777770F
253CS5PCR_D:	.long	0x77000000
254CS6PCR_D:	.long	0x77000000
255ICR0_D:		.long	0x00E00000
256MIM8_D:		.long	0x00000000
257MIMC_D1:	.long	0x01d10008
258MIMC_D2:	.long	0x01d10009
259MIMC_D3:	.long	0x01d10209
260SCR4_D1:	.long	0x00000001
261SCR4_D2:	.long	0x00000002
262SCR4_D3:	.long	0x00000003
263SCR4_D4:	.long	0x00000004
264STRC_D:		.long	0x000f3980
265SDR4_D:		.long	0x00000300
266SDMR00308_D:	.long	0x00000000
267SDMR00B08_D:	.long	0x00000000
268SDMR02000_D:	.long	0x00000000
269PSEL0_D:	.long	0x00000001
270PSEL1_D:	.long	0x00000244
271SR_MASK_D:	.long	0xEFFFFF0F
272WDTST_D:	.long	0x5A000FFF
273WDTCSR_D:	.long	0xA5000000
274WDTBST_D:	.long	0x55000000
275