1/*
2 * Copyright (C) 2008 Renesas Solutions Corp.
3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
4 * Copyright (C) 2007 Kenati Technologies, Inc.
5 *
6 * board/sh7763rdp/lowlevel_init.S
7 *
8 * SPDX-License-Identifier:	GPL-2.0+
9 */
10
11#include <config.h>
12#include <version.h>
13
14#include <asm/processor.h>
15#include <asm/macro.h>
16
17	.global	lowlevel_init
18
19	.text
20	.align	2
21
22lowlevel_init:
23
24	write32	WDTCSR_A, WDTCSR_D	/* Watchdog Control / Status Register */
25
26	write32	WDTST_A, WDTST_D	/* Watchdog Stop Time Register */
27
28	write32	WDTBST_A, WDTBST_D	/*
29					 * 0xFFCC0008
30					 * Watchdog Base Stop Time Register
31					 */
32
33	write32	CCR_A, CCR_CACHE_ICI_D	/* Address of Cache Control Register */
34					/* Instruction Cache Invalidate */
35
36	write32	MMUCR_A, MMU_CONTROL_TI_D	/* MMU Control Register */
37						/* TI == TLB Invalidate bit */
38
39	write32	MSTPCR0_A, MSTPCR0_D	/* Address of Power Control Register 0 */
40
41	write32	MSTPCR1_A, MSTPCR1_D	/* Address of Power Control Register 1 */
42
43	write32	RAMCR_A, RAMCR_D
44
45	mov.l	MMSELR_A, r1
46	mov.l	MMSELR_D, r0
47	synco
48	mov.l	r0, @r1
49
50	mov.l	@r1, r2		/* execute two reads after setting MMSELR */
51	mov.l	@r1, r2
52	synco
53
54	/* issue memory read */
55	mov.l	DDRSD_START_A, r1	/* memory address to read*/
56	mov.l	@r1, r0
57	synco
58
59	write32	MIM8_A, MIM8_D
60
61	write32	MIMC_A, MIMC_D1
62
63	write32	STRC_A, STRC_D
64
65	write32	SDR4_A, SDR4_D
66
67	write32	MIMC_A, MIMC_D2
68
69	nop
70	nop
71	nop
72
73	write32	SCR4_A, SCR4_D3
74
75	write32	SCR4_A, SCR4_D2
76
77	write32	SDMR02000_A, SDMR02000_D
78
79	write32	SDMR00B08_A, SDMR00B08_D
80
81	write32	SCR4_A, SCR4_D2
82
83	write32	SCR4_A, SCR4_D4
84
85	nop
86	nop
87	nop
88	nop
89
90	write32	SCR4_A, SCR4_D4
91
92	nop
93	nop
94	nop
95	nop
96
97	write32	SDMR00308_A, SDMR00308_D
98
99	write32	MIMC_A, MIMC_D3
100
101	mov.l	SCR4_A, r1
102	mov.l	SCR4_D1, r0
103	mov.l	DELAY60_D, r3
104
105delay_loop_60:
106	mov.l	r0, @r1
107	dt	r3
108	bf	delay_loop_60
109	nop
110
111	write32	CCR_A, CCR_CACHE_D_2	/* Address of Cache Control Register */
112
113bsc_init:
114	write32	BCR_A, BCR_D
115
116	write32	CS0BCR_A, CS0BCR_D
117
118	write32	CS1BCR_A, CS1BCR_D
119
120	write32	CS2BCR_A, CS2BCR_D
121
122	write32	CS4BCR_A, CS4BCR_D
123
124	write32	CS5BCR_A, CS5BCR_D
125
126	write32	CS6BCR_A, CS6BCR_D
127
128	write32	CS0WCR_A, CS0WCR_D
129
130	write32	CS1WCR_A, CS1WCR_D
131
132	write32	CS2WCR_A, CS2WCR_D
133
134	write32	CS4WCR_A, CS4WCR_D
135
136	write32	CS5WCR_A, CS5WCR_D
137
138	write32	CS6WCR_A, CS6WCR_D
139
140	write32	CS5PCR_A, CS5PCR_D
141
142	write32	CS6PCR_A, CS6PCR_D
143
144	mov.l	DELAY200_D, r3
145
146delay_loop_200:
147	dt	r3
148	bf	delay_loop_200
149	nop
150
151	write16	PSEL0_A, PSEL0_D
152
153	write16	PSEL1_A, PSEL1_D
154
155	write32	ICR0_A, ICR0_D
156
157	stc sr, r0	/* BL bit off(init=ON) */
158	mov.l	SR_MASK_D, r1
159	and r1, r0
160	ldc r0, sr
161
162	rts
163	nop
164
165	.align	2
166
167DELAY60_D:	.long	60
168DELAY200_D:	.long	17800
169
170CCR_A:		.long	0xFF00001C
171MMUCR_A:	.long	0xFF000010
172RAMCR_A:	.long	0xFF000074
173
174/* Low power mode control */
175MSTPCR0_A:	.long	0xFFC80030
176MSTPCR1_A:	.long	0xFFC80038
177
178/* RWBT */
179WDTST_A:	.long	0xFFCC0000
180WDTCSR_A:	.long	0xFFCC0004
181WDTBST_A:	.long	0xFFCC0008
182
183/* BSC */
184MMSELR_A:	.long	0xFE600020
185BCR_A:		.long	0xFF801000
186CS0BCR_A:	.long	0xFF802000
187CS1BCR_A:	.long	0xFF802010
188CS2BCR_A:	.long	0xFF802020
189CS4BCR_A:	.long	0xFF802040
190CS5BCR_A:	.long	0xFF802050
191CS6BCR_A:	.long	0xFF802060
192CS0WCR_A:	.long	0xFF802008
193CS1WCR_A:	.long	0xFF802018
194CS2WCR_A:	.long	0xFF802028
195CS4WCR_A:	.long	0xFF802048
196CS5WCR_A:	.long	0xFF802058
197CS6WCR_A:	.long	0xFF802068
198CS5PCR_A:	.long	0xFF802070
199CS6PCR_A:	.long	0xFF802080
200DDRSD_START_A:	.long	0xAC000000
201
202/* INTC */
203ICR0_A:		.long	0xFFD00000
204
205/* DDR I/F */
206MIM8_A:		.long	0xFE800008
207MIMC_A:		.long	0xFE80000C
208SCR4_A:		.long	0xFE800014
209STRC_A:		.long	0xFE80001C
210SDR4_A:		.long	0xFE800034
211SDMR00308_A:	.long	0xFE900308
212SDMR00B08_A:	.long	0xFE900B08
213SDMR02000_A:	.long	0xFE902000
214
215/* GPIO */
216PSEL0_A:	.long	0xFFEF0070
217PSEL1_A:	.long	0xFFEF0072
218
219CCR_CACHE_ICI_D:.long	0x00000800
220CCR_CACHE_D_2:	.long	0x00000103
221MMU_CONTROL_TI_D:.long	0x00000004
222RAMCR_D:	.long	0x00000200
223MSTPCR0_D:	.long	0x00000000
224MSTPCR1_D:	.long	0x00000000
225
226MMSELR_D:	.long	0xa5a50000
227BCR_D:		.long	0x00000000
228CS0BCR_D:	.long	0x77777770
229CS1BCR_D:	.long	0x77777670
230CS2BCR_D:	.long	0x77777670
231CS4BCR_D:	.long	0x77777670
232CS5BCR_D:	.long	0x77777670
233CS6BCR_D:	.long	0x77777670
234CS0WCR_D:	.long	0x7777770F
235CS1WCR_D:	.long	0x22000002
236CS2WCR_D:	.long	0x7777770F
237CS4WCR_D:	.long	0x7777770F
238CS5WCR_D:	.long	0x7777770F
239CS6WCR_D:	.long	0x7777770F
240CS5PCR_D:	.long	0x77000000
241CS6PCR_D:	.long	0x77000000
242ICR0_D:		.long	0x00E00000
243MIM8_D:		.long	0x00000000
244MIMC_D1:	.long	0x01d10008
245MIMC_D2:	.long	0x01d10009
246MIMC_D3:	.long	0x01d10209
247SCR4_D1:	.long	0x00000001
248SCR4_D2:	.long	0x00000002
249SCR4_D3:	.long	0x00000003
250SCR4_D4:	.long	0x00000004
251STRC_D:		.long	0x000f3980
252SDR4_D:		.long	0x00000300
253SDMR00308_D:	.long	0x00000000
254SDMR00B08_D:	.long	0x00000000
255SDMR02000_D:	.long	0x00000000
256PSEL0_D:	.word	0x00000001
257PSEL1_D:	.word	0x00000244
258SR_MASK_D:	.long	0xEFFFFF0F
259WDTST_D:	.long	0x5A000FFF
260WDTCSR_D:	.long	0xA5000000
261WDTBST_D:	.long	0x55000000
262