1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <environment.h> 9 #include <malloc.h> 10 #include <asm/processor.h> 11 #include <asm/io.h> 12 #include <asm/mmc.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 16 int checkboard(void) 17 { 18 puts("BOARD: R0P7757LC0030RL board\n"); 19 20 return 0; 21 } 22 23 static void init_gctrl(void) 24 { 25 struct gctrl_regs *gctrl = GCTRL_BASE; 26 unsigned long graofst; 27 28 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; 29 writel(graofst | 0x20000f00, &gctrl->gracr3); 30 } 31 32 static int init_pcie_bridge_from_spi(void *buf, size_t size) 33 { 34 struct spi_flash *spi; 35 int ret; 36 unsigned long pcie_addr; 37 38 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 39 if (!spi) { 40 printf("%s: spi_flash probe error.\n", __func__); 41 return 1; 42 } 43 44 if (is_sh7757_b0()) 45 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0; 46 else 47 pcie_addr = SH7757LCR_PCIEBRG_ADDR; 48 49 ret = spi_flash_read(spi, pcie_addr, size, buf); 50 if (ret) { 51 printf("%s: spi_flash read error.\n", __func__); 52 spi_flash_free(spi); 53 return 1; 54 } 55 spi_flash_free(spi); 56 57 return 0; 58 } 59 60 static void init_pcie_bridge(void) 61 { 62 struct pciebrg_regs *pciebrg = PCIEBRG_BASE; 63 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; 64 int i; 65 unsigned char *data; 66 unsigned short tmp; 67 unsigned long pcie_size; 68 69 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) 70 return; 71 72 if (is_sh7757_b0()) 73 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0; 74 else 75 pcie_size = SH7757LCR_PCIEBRG_SIZE; 76 77 data = malloc(pcie_size); 78 if (!data) { 79 printf("%s: malloc error.\n", __func__); 80 return; 81 } 82 if (init_pcie_bridge_from_spi(data, pcie_size)) { 83 free(data); 84 return; 85 } 86 87 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && 88 data[3] == 0xff) { 89 free(data); 90 printf("%s: skipped initialization\n", __func__); 91 return; 92 } 93 94 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ 95 writew(0x0000, &pciebrg->cp_ctrl); 96 writew(0x0000, &pciebrg->cp_addr); 97 98 for (i = 0; i < pcie_size; i += 2) { 99 tmp = (data[i] << 8) | data[i + 1]; 100 writew(tmp, &pciebrg->cp_data); 101 } 102 103 writew(0xa500, &pciebrg->ctrl_h8s); /* start */ 104 if (!is_sh7757_b0()) 105 writel(0x00000001, &pcie_setup->pbictl3); 106 107 free(data); 108 } 109 110 static void init_usb_phy(void) 111 { 112 struct usb_common_regs *common0 = USB0_COMMON_BASE; 113 struct usb_common_regs *common1 = USB1_COMMON_BASE; 114 struct usb0_phy_regs *phy = USB0_PHY_BASE; 115 struct usb1_port_regs *port = USB1_PORT_BASE; 116 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; 117 118 writew(0x0100, &phy->reset); /* set reset */ 119 /* port0 = USB0, port1 = USB1 */ 120 writew(0x0002, &phy->portsel); 121 writel(0x0001, &port->port1sel); /* port1 = Host */ 122 writew(0x0111, &phy->reset); /* clear reset */ 123 124 writew(0x4000, &common0->suspmode); 125 writew(0x4000, &common1->suspmode); 126 127 #if defined(__LITTLE_ENDIAN) 128 writel(0x00000000, &align->ehcidatac); 129 writel(0x00000000, &align->ohcidatac); 130 #endif 131 } 132 133 static void set_mac_to_sh_eth_register(int channel, char *mac_string) 134 { 135 struct ether_mac_regs *ether; 136 unsigned char mac[6]; 137 unsigned long val; 138 139 eth_parse_enetaddr(mac_string, mac); 140 141 if (!channel) 142 ether = ETHER0_MAC_BASE; 143 else 144 ether = ETHER1_MAC_BASE; 145 146 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 147 writel(val, ðer->mahr); 148 val = (mac[4] << 8) | mac[5]; 149 writel(val, ðer->malr); 150 } 151 152 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) 153 { 154 struct ether_mac_regs *ether; 155 unsigned char mac[6]; 156 unsigned long val; 157 158 eth_parse_enetaddr(mac_string, mac); 159 160 if (!channel) 161 ether = GETHER0_MAC_BASE; 162 else 163 ether = GETHER1_MAC_BASE; 164 165 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 166 writel(val, ðer->mahr); 167 val = (mac[4] << 8) | mac[5]; 168 writel(val, ðer->malr); 169 } 170 171 /***************************************************************** 172 * This PMB must be set on this timing. The lowlevel_init is run on 173 * Area 0(phys 0x00000000), so we have to map it. 174 * 175 * The new PMB table is following: 176 * ent virt phys v sz c wt 177 * 0 0xa0000000 0x40000000 1 128M 0 1 178 * 1 0xa8000000 0x48000000 1 128M 0 1 179 * 2 0xb0000000 0x50000000 1 128M 0 1 180 * 3 0xb8000000 0x58000000 1 128M 0 1 181 * 4 0x80000000 0x40000000 1 128M 1 1 182 * 5 0x88000000 0x48000000 1 128M 1 1 183 * 6 0x90000000 0x50000000 1 128M 1 1 184 * 7 0x98000000 0x58000000 1 128M 1 1 185 */ 186 static void set_pmb_on_board_init(void) 187 { 188 struct mmu_regs *mmu = MMU_BASE; 189 190 /* clear ITLB */ 191 writel(0x00000004, &mmu->mmucr); 192 193 /* delete PMB for SPIBOOT */ 194 writel(0, PMB_ADDR_BASE(0)); 195 writel(0, PMB_DATA_BASE(0)); 196 197 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ 198 /* ppn ub v s1 s0 c wt */ 199 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); 200 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); 201 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); 202 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); 203 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); 204 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); 205 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); 206 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); 207 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); 208 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); 209 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); 210 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); 211 } 212 213 int board_init(void) 214 { 215 struct gether_control_regs *gether = GETHER_CONTROL_BASE; 216 217 set_pmb_on_board_init(); 218 219 /* enable RMII's MDIO (disable GRMII's MDIO) */ 220 writel(0x00030000, &gether->gbecont); 221 222 init_gctrl(); 223 init_usb_phy(); 224 225 return 0; 226 } 227 228 int board_mmc_init(bd_t *bis) 229 { 230 return mmcif_mmc_init(); 231 } 232 233 static int get_sh_eth_mac_raw(unsigned char *buf, int size) 234 { 235 struct spi_flash *spi; 236 int ret; 237 238 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 239 if (spi == NULL) { 240 printf("%s: spi_flash probe error.\n", __func__); 241 return 1; 242 } 243 244 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf); 245 if (ret) { 246 printf("%s: spi_flash read error.\n", __func__); 247 spi_flash_free(spi); 248 return 1; 249 } 250 spi_flash_free(spi); 251 252 return 0; 253 } 254 255 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) 256 { 257 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)], 258 SH7757LCR_ETHERNET_MAC_SIZE); 259 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ 260 261 return 0; 262 } 263 264 static void init_ethernet_mac(void) 265 { 266 char mac_string[64]; 267 char env_string[64]; 268 int i; 269 unsigned char *buf; 270 271 buf = malloc(256); 272 if (!buf) { 273 printf("%s: malloc error.\n", __func__); 274 return; 275 } 276 get_sh_eth_mac_raw(buf, 256); 277 278 /* Fast Ethernet */ 279 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) { 280 get_sh_eth_mac(i, mac_string, buf); 281 if (i == 0) 282 env_set("ethaddr", mac_string); 283 else { 284 sprintf(env_string, "eth%daddr", i); 285 env_set(env_string, mac_string); 286 } 287 288 set_mac_to_sh_eth_register(i, mac_string); 289 } 290 291 /* Gigabit Ethernet */ 292 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) { 293 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf); 294 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH); 295 env_set(env_string, mac_string); 296 297 set_mac_to_sh_giga_eth_register(i, mac_string); 298 } 299 300 free(buf); 301 } 302 303 static void init_pcie(void) 304 { 305 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; 306 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE; 307 308 writel(0x00000ff2, &pcie_setup->ladmsk0); 309 writel(0x00000001, &pcie_setup->barmap); 310 writel(0xffcaa000, &pcie_setup->lad0); 311 writel(0x00030000, &pcie_sysbus->endictl0); 312 writel(0x00000003, &pcie_sysbus->endictl1); 313 writel(0x00000004, &pcie_setup->pbictl2); 314 } 315 316 static void finish_spiboot(void) 317 { 318 struct gctrl_regs *gctrl = GCTRL_BASE; 319 /* 320 * SH7757 B0 does not use LBSC. 321 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0. 322 * This setting is not cleared by manual reset, So we have to set it 323 * to 0. 324 */ 325 writel(0x00000000, &gctrl->spibootcan); 326 } 327 328 int board_late_init(void) 329 { 330 init_ethernet_mac(); 331 init_pcie_bridge(); 332 init_pcie(); 333 finish_spiboot(); 334 335 return 0; 336 } 337 338 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 339 { 340 struct gctrl_regs *gctrl = GCTRL_BASE; 341 unsigned long graofst; 342 343 writel(0xfedcba98, &gctrl->wprotect); 344 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; 345 writel(graofst | 0xa0000f00, &gctrl->gracr3); 346 347 return 0; 348 } 349 350 U_BOOT_CMD( 351 sh_g200, 1, 1, do_sh_g200, 352 "enable sh-g200", 353 "enable SH-G200 bus (disable PCIe-G200)" 354 ); 355 356 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 357 { 358 int i, ret; 359 char mac_string[256]; 360 struct spi_flash *spi; 361 unsigned char *buf; 362 363 if (argc != 5) { 364 buf = malloc(256); 365 if (!buf) { 366 printf("%s: malloc error.\n", __func__); 367 return 1; 368 } 369 370 get_sh_eth_mac_raw(buf, 256); 371 372 /* print current MAC address */ 373 for (i = 0; i < 4; i++) { 374 get_sh_eth_mac(i, mac_string, buf); 375 if (i < 2) 376 printf(" ETHERC ch%d = %s\n", i, mac_string); 377 else 378 printf("GETHERC ch%d = %s\n", i-2, mac_string); 379 } 380 free(buf); 381 return 0; 382 } 383 384 /* new setting */ 385 memset(mac_string, 0xff, sizeof(mac_string)); 386 sprintf(mac_string, "%s\t%s\t%s\t%s", 387 argv[1], argv[2], argv[3], argv[4]); 388 389 /* write MAC data to SPI rom */ 390 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 391 if (!spi) { 392 printf("%s: spi_flash probe error.\n", __func__); 393 return 1; 394 } 395 396 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, 397 SH7757LCR_SPI_SECTOR_SIZE); 398 if (ret) { 399 printf("%s: spi_flash erase error.\n", __func__); 400 return 1; 401 } 402 403 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, 404 sizeof(mac_string), mac_string); 405 if (ret) { 406 printf("%s: spi_flash write error.\n", __func__); 407 spi_flash_free(spi); 408 return 1; 409 } 410 spi_flash_free(spi); 411 412 puts("The writing of the MAC address to SPI ROM was completed.\n"); 413 414 return 0; 415 } 416 417 U_BOOT_CMD( 418 write_mac, 5, 1, do_write_mac, 419 "write MAC address for ETHERC/GETHERC", 420 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" 421 ); 422