1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <malloc.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include <spi_flash.h> 28 29 int checkboard(void) 30 { 31 puts("BOARD: R0P7757LC0030RL board\n"); 32 33 return 0; 34 } 35 36 static void init_gctrl(void) 37 { 38 struct gctrl_regs *gctrl = GCTRL_BASE; 39 unsigned long graofst; 40 41 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; 42 writel(graofst | 0x20000f00, &gctrl->gracr3); 43 } 44 45 static int init_pcie_bridge_from_spi(void *buf, size_t size) 46 { 47 struct spi_flash *spi; 48 int ret; 49 unsigned long pcie_addr; 50 51 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 52 if (!spi) { 53 printf("%s: spi_flash probe error.\n", __func__); 54 return 1; 55 } 56 57 if (is_sh7757_b0()) 58 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0; 59 else 60 pcie_addr = SH7757LCR_PCIEBRG_ADDR; 61 62 ret = spi_flash_read(spi, pcie_addr, size, buf); 63 if (ret) { 64 printf("%s: spi_flash read error.\n", __func__); 65 spi_flash_free(spi); 66 return 1; 67 } 68 spi_flash_free(spi); 69 70 return 0; 71 } 72 73 static void init_pcie_bridge(void) 74 { 75 struct pciebrg_regs *pciebrg = PCIEBRG_BASE; 76 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; 77 int i; 78 unsigned char *data; 79 unsigned short tmp; 80 unsigned long pcie_size; 81 82 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) 83 return; 84 85 if (is_sh7757_b0()) 86 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0; 87 else 88 pcie_size = SH7757LCR_PCIEBRG_SIZE; 89 90 data = malloc(pcie_size); 91 if (!data) { 92 printf("%s: malloc error.\n", __func__); 93 return; 94 } 95 if (init_pcie_bridge_from_spi(data, pcie_size)) { 96 free(data); 97 return; 98 } 99 100 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && 101 data[3] == 0xff) { 102 free(data); 103 printf("%s: skipped initialization\n", __func__); 104 return; 105 } 106 107 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ 108 writew(0x0000, &pciebrg->cp_ctrl); 109 writew(0x0000, &pciebrg->cp_addr); 110 111 for (i = 0; i < pcie_size; i += 2) { 112 tmp = (data[i] << 8) | data[i + 1]; 113 writew(tmp, &pciebrg->cp_data); 114 } 115 116 writew(0xa500, &pciebrg->ctrl_h8s); /* start */ 117 if (!is_sh7757_b0()) 118 writel(0x00000001, &pcie_setup->pbictl3); 119 120 free(data); 121 } 122 123 static void init_usb_phy(void) 124 { 125 struct usb_common_regs *common0 = USB0_COMMON_BASE; 126 struct usb_common_regs *common1 = USB1_COMMON_BASE; 127 struct usb0_phy_regs *phy = USB0_PHY_BASE; 128 struct usb1_port_regs *port = USB1_PORT_BASE; 129 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; 130 131 writew(0x0100, &phy->reset); /* set reset */ 132 /* port0 = USB0, port1 = USB1 */ 133 writew(0x0002, &phy->portsel); 134 writel(0x0001, &port->port1sel); /* port1 = Host */ 135 writew(0x0111, &phy->reset); /* clear reset */ 136 137 writew(0x4000, &common0->suspmode); 138 writew(0x4000, &common1->suspmode); 139 140 #if defined(__LITTLE_ENDIAN) 141 writel(0x00000000, &align->ehcidatac); 142 writel(0x00000000, &align->ohcidatac); 143 #endif 144 } 145 146 static void set_mac_to_sh_eth_register(int channel, char *mac_string) 147 { 148 struct ether_mac_regs *ether; 149 unsigned char mac[6]; 150 unsigned long val; 151 152 eth_parse_enetaddr(mac_string, mac); 153 154 if (!channel) 155 ether = ETHER0_MAC_BASE; 156 else 157 ether = ETHER1_MAC_BASE; 158 159 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 160 writel(val, ðer->mahr); 161 val = (mac[4] << 8) | mac[5]; 162 writel(val, ðer->malr); 163 } 164 165 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) 166 { 167 struct ether_mac_regs *ether; 168 unsigned char mac[6]; 169 unsigned long val; 170 171 eth_parse_enetaddr(mac_string, mac); 172 173 if (!channel) 174 ether = GETHER0_MAC_BASE; 175 else 176 ether = GETHER1_MAC_BASE; 177 178 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 179 writel(val, ðer->mahr); 180 val = (mac[4] << 8) | mac[5]; 181 writel(val, ðer->malr); 182 } 183 184 /***************************************************************** 185 * This PMB must be set on this timing. The lowlevel_init is run on 186 * Area 0(phys 0x00000000), so we have to map it. 187 * 188 * The new PMB table is following: 189 * ent virt phys v sz c wt 190 * 0 0xa0000000 0x40000000 1 128M 0 1 191 * 1 0xa8000000 0x48000000 1 128M 0 1 192 * 2 0xb0000000 0x50000000 1 128M 0 1 193 * 3 0xb8000000 0x58000000 1 128M 0 1 194 * 4 0x80000000 0x40000000 1 128M 1 1 195 * 5 0x88000000 0x48000000 1 128M 1 1 196 * 6 0x90000000 0x50000000 1 128M 1 1 197 * 7 0x98000000 0x58000000 1 128M 1 1 198 */ 199 static void set_pmb_on_board_init(void) 200 { 201 struct mmu_regs *mmu = MMU_BASE; 202 203 /* clear ITLB */ 204 writel(0x00000004, &mmu->mmucr); 205 206 /* delete PMB for SPIBOOT */ 207 writel(0, PMB_ADDR_BASE(0)); 208 writel(0, PMB_DATA_BASE(0)); 209 210 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ 211 /* ppn ub v s1 s0 c wt */ 212 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); 213 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); 214 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); 215 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); 216 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); 217 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); 218 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); 219 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); 220 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); 221 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); 222 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); 223 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); 224 } 225 226 int board_init(void) 227 { 228 struct gether_control_regs *gether = GETHER_CONTROL_BASE; 229 230 set_pmb_on_board_init(); 231 232 /* enable RMII's MDIO (disable GRMII's MDIO) */ 233 writel(0x00030000, &gether->gbecont); 234 235 init_gctrl(); 236 init_usb_phy(); 237 238 return 0; 239 } 240 241 int dram_init(void) 242 { 243 DECLARE_GLOBAL_DATA_PTR; 244 245 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 246 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 247 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 248 printf(" Physical address\n"); 249 printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n", 250 SH7757LCR_SDRAM_PHYS_TOP, 251 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1); 252 printf(" 0x%08x - 0x%08x : No Access Area\n", 253 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE, 254 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1); 255 printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n", 256 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2, 257 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 + 258 SH7757LCR_SDRAM_DVC_SIZE - 1); 259 printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n", 260 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET, 261 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff); 262 263 return 0; 264 } 265 266 static int get_sh_eth_mac_raw(unsigned char *buf, int size) 267 { 268 struct spi_flash *spi; 269 int ret; 270 271 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 272 if (spi == NULL) { 273 printf("%s: spi_flash probe error.\n", __func__); 274 return 1; 275 } 276 277 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf); 278 if (ret) { 279 printf("%s: spi_flash read error.\n", __func__); 280 spi_flash_free(spi); 281 return 1; 282 } 283 spi_flash_free(spi); 284 285 return 0; 286 } 287 288 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) 289 { 290 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)], 291 SH7757LCR_ETHERNET_MAC_SIZE); 292 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ 293 294 return 0; 295 } 296 297 static void init_ethernet_mac(void) 298 { 299 char mac_string[64]; 300 char env_string[64]; 301 int i; 302 unsigned char *buf; 303 304 buf = malloc(256); 305 if (!buf) { 306 printf("%s: malloc error.\n", __func__); 307 return; 308 } 309 get_sh_eth_mac_raw(buf, 256); 310 311 /* Fast Ethernet */ 312 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) { 313 get_sh_eth_mac(i, mac_string, buf); 314 if (i == 0) 315 setenv("ethaddr", mac_string); 316 else { 317 sprintf(env_string, "eth%daddr", i); 318 setenv(env_string, mac_string); 319 } 320 321 set_mac_to_sh_eth_register(i, mac_string); 322 } 323 324 /* Gigabit Ethernet */ 325 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) { 326 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf); 327 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH); 328 setenv(env_string, mac_string); 329 330 set_mac_to_sh_giga_eth_register(i, mac_string); 331 } 332 333 free(buf); 334 } 335 336 static void init_pcie(void) 337 { 338 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; 339 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE; 340 341 writel(0x00000ff2, &pcie_setup->ladmsk0); 342 writel(0x00000001, &pcie_setup->barmap); 343 writel(0xffcaa000, &pcie_setup->lad0); 344 writel(0x00030000, &pcie_sysbus->endictl0); 345 writel(0x00000003, &pcie_sysbus->endictl1); 346 writel(0x00000004, &pcie_setup->pbictl2); 347 } 348 349 static void finish_spiboot(void) 350 { 351 struct gctrl_regs *gctrl = GCTRL_BASE; 352 /* 353 * SH7757 B0 does not use LBSC. 354 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0. 355 * This setting is not cleared by manual reset, So we have to set it 356 * to 0. 357 */ 358 writel(0x00000000, &gctrl->spibootcan); 359 } 360 361 int board_late_init(void) 362 { 363 init_ethernet_mac(); 364 init_pcie_bridge(); 365 init_pcie(); 366 finish_spiboot(); 367 368 return 0; 369 } 370 371 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 372 { 373 struct gctrl_regs *gctrl = GCTRL_BASE; 374 unsigned long graofst; 375 376 writel(0xfedcba98, &gctrl->wprotect); 377 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; 378 writel(graofst | 0xa0000f00, &gctrl->gracr3); 379 380 return 0; 381 } 382 383 U_BOOT_CMD( 384 sh_g200, 1, 1, do_sh_g200, 385 "enable sh-g200", 386 "enable SH-G200 bus (disable PCIe-G200)" 387 ); 388 389 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 390 { 391 int i, ret; 392 char mac_string[256]; 393 struct spi_flash *spi; 394 unsigned char *buf; 395 396 if (argc != 5) { 397 buf = malloc(256); 398 if (!buf) { 399 printf("%s: malloc error.\n", __func__); 400 return 1; 401 } 402 403 get_sh_eth_mac_raw(buf, 256); 404 405 /* print current MAC address */ 406 for (i = 0; i < 4; i++) { 407 get_sh_eth_mac(i, mac_string, buf); 408 if (i < 2) 409 printf(" ETHERC ch%d = %s\n", i, mac_string); 410 else 411 printf("GETHERC ch%d = %s\n", i-2, mac_string); 412 } 413 free(buf); 414 return 0; 415 } 416 417 /* new setting */ 418 memset(mac_string, 0xff, sizeof(mac_string)); 419 sprintf(mac_string, "%s\t%s\t%s\t%s", 420 argv[1], argv[2], argv[3], argv[4]); 421 422 /* write MAC data to SPI rom */ 423 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 424 if (!spi) { 425 printf("%s: spi_flash probe error.\n", __func__); 426 return 1; 427 } 428 429 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, 430 SH7757LCR_SPI_SECTOR_SIZE); 431 if (ret) { 432 printf("%s: spi_flash erase error.\n", __func__); 433 return 1; 434 } 435 436 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, 437 sizeof(mac_string), mac_string); 438 if (ret) { 439 printf("%s: spi_flash write error.\n", __func__); 440 spi_flash_free(spi); 441 return 1; 442 } 443 spi_flash_free(spi); 444 445 puts("The writing of the MAC address to SPI ROM was completed.\n"); 446 447 return 0; 448 } 449 450 U_BOOT_CMD( 451 write_mac, 5, 1, do_write_mac, 452 "write MAC address for ETHERC/GETHERC", 453 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" 454 ); 455