1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <asm/processor.h> 10 #include <asm/io.h> 11 #include <asm/mmc.h> 12 #include <spi.h> 13 #include <spi_flash.h> 14 15 int checkboard(void) 16 { 17 puts("BOARD: R0P7757LC0030RL board\n"); 18 19 return 0; 20 } 21 22 static void init_gctrl(void) 23 { 24 struct gctrl_regs *gctrl = GCTRL_BASE; 25 unsigned long graofst; 26 27 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; 28 writel(graofst | 0x20000f00, &gctrl->gracr3); 29 } 30 31 static int init_pcie_bridge_from_spi(void *buf, size_t size) 32 { 33 struct spi_flash *spi; 34 int ret; 35 unsigned long pcie_addr; 36 37 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 38 if (!spi) { 39 printf("%s: spi_flash probe error.\n", __func__); 40 return 1; 41 } 42 43 if (is_sh7757_b0()) 44 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0; 45 else 46 pcie_addr = SH7757LCR_PCIEBRG_ADDR; 47 48 ret = spi_flash_read(spi, pcie_addr, size, buf); 49 if (ret) { 50 printf("%s: spi_flash read error.\n", __func__); 51 spi_flash_free(spi); 52 return 1; 53 } 54 spi_flash_free(spi); 55 56 return 0; 57 } 58 59 static void init_pcie_bridge(void) 60 { 61 struct pciebrg_regs *pciebrg = PCIEBRG_BASE; 62 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; 63 int i; 64 unsigned char *data; 65 unsigned short tmp; 66 unsigned long pcie_size; 67 68 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) 69 return; 70 71 if (is_sh7757_b0()) 72 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0; 73 else 74 pcie_size = SH7757LCR_PCIEBRG_SIZE; 75 76 data = malloc(pcie_size); 77 if (!data) { 78 printf("%s: malloc error.\n", __func__); 79 return; 80 } 81 if (init_pcie_bridge_from_spi(data, pcie_size)) { 82 free(data); 83 return; 84 } 85 86 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && 87 data[3] == 0xff) { 88 free(data); 89 printf("%s: skipped initialization\n", __func__); 90 return; 91 } 92 93 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ 94 writew(0x0000, &pciebrg->cp_ctrl); 95 writew(0x0000, &pciebrg->cp_addr); 96 97 for (i = 0; i < pcie_size; i += 2) { 98 tmp = (data[i] << 8) | data[i + 1]; 99 writew(tmp, &pciebrg->cp_data); 100 } 101 102 writew(0xa500, &pciebrg->ctrl_h8s); /* start */ 103 if (!is_sh7757_b0()) 104 writel(0x00000001, &pcie_setup->pbictl3); 105 106 free(data); 107 } 108 109 static void init_usb_phy(void) 110 { 111 struct usb_common_regs *common0 = USB0_COMMON_BASE; 112 struct usb_common_regs *common1 = USB1_COMMON_BASE; 113 struct usb0_phy_regs *phy = USB0_PHY_BASE; 114 struct usb1_port_regs *port = USB1_PORT_BASE; 115 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; 116 117 writew(0x0100, &phy->reset); /* set reset */ 118 /* port0 = USB0, port1 = USB1 */ 119 writew(0x0002, &phy->portsel); 120 writel(0x0001, &port->port1sel); /* port1 = Host */ 121 writew(0x0111, &phy->reset); /* clear reset */ 122 123 writew(0x4000, &common0->suspmode); 124 writew(0x4000, &common1->suspmode); 125 126 #if defined(__LITTLE_ENDIAN) 127 writel(0x00000000, &align->ehcidatac); 128 writel(0x00000000, &align->ohcidatac); 129 #endif 130 } 131 132 static void set_mac_to_sh_eth_register(int channel, char *mac_string) 133 { 134 struct ether_mac_regs *ether; 135 unsigned char mac[6]; 136 unsigned long val; 137 138 eth_parse_enetaddr(mac_string, mac); 139 140 if (!channel) 141 ether = ETHER0_MAC_BASE; 142 else 143 ether = ETHER1_MAC_BASE; 144 145 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 146 writel(val, ðer->mahr); 147 val = (mac[4] << 8) | mac[5]; 148 writel(val, ðer->malr); 149 } 150 151 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) 152 { 153 struct ether_mac_regs *ether; 154 unsigned char mac[6]; 155 unsigned long val; 156 157 eth_parse_enetaddr(mac_string, mac); 158 159 if (!channel) 160 ether = GETHER0_MAC_BASE; 161 else 162 ether = GETHER1_MAC_BASE; 163 164 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 165 writel(val, ðer->mahr); 166 val = (mac[4] << 8) | mac[5]; 167 writel(val, ðer->malr); 168 } 169 170 /***************************************************************** 171 * This PMB must be set on this timing. The lowlevel_init is run on 172 * Area 0(phys 0x00000000), so we have to map it. 173 * 174 * The new PMB table is following: 175 * ent virt phys v sz c wt 176 * 0 0xa0000000 0x40000000 1 128M 0 1 177 * 1 0xa8000000 0x48000000 1 128M 0 1 178 * 2 0xb0000000 0x50000000 1 128M 0 1 179 * 3 0xb8000000 0x58000000 1 128M 0 1 180 * 4 0x80000000 0x40000000 1 128M 1 1 181 * 5 0x88000000 0x48000000 1 128M 1 1 182 * 6 0x90000000 0x50000000 1 128M 1 1 183 * 7 0x98000000 0x58000000 1 128M 1 1 184 */ 185 static void set_pmb_on_board_init(void) 186 { 187 struct mmu_regs *mmu = MMU_BASE; 188 189 /* clear ITLB */ 190 writel(0x00000004, &mmu->mmucr); 191 192 /* delete PMB for SPIBOOT */ 193 writel(0, PMB_ADDR_BASE(0)); 194 writel(0, PMB_DATA_BASE(0)); 195 196 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ 197 /* ppn ub v s1 s0 c wt */ 198 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); 199 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); 200 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); 201 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); 202 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); 203 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); 204 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); 205 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); 206 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); 207 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); 208 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); 209 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); 210 } 211 212 int board_init(void) 213 { 214 struct gether_control_regs *gether = GETHER_CONTROL_BASE; 215 216 set_pmb_on_board_init(); 217 218 /* enable RMII's MDIO (disable GRMII's MDIO) */ 219 writel(0x00030000, &gether->gbecont); 220 221 init_gctrl(); 222 init_usb_phy(); 223 224 return 0; 225 } 226 227 int dram_init(void) 228 { 229 DECLARE_GLOBAL_DATA_PTR; 230 231 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 232 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 233 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 234 printf(" Physical address\n"); 235 printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n", 236 SH7757LCR_SDRAM_PHYS_TOP, 237 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1); 238 printf(" 0x%08x - 0x%08x : No Access Area\n", 239 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE, 240 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1); 241 printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n", 242 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2, 243 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 + 244 SH7757LCR_SDRAM_DVC_SIZE - 1); 245 printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n", 246 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET, 247 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff); 248 249 return 0; 250 } 251 252 int board_mmc_init(bd_t *bis) 253 { 254 return mmcif_mmc_init(); 255 } 256 257 static int get_sh_eth_mac_raw(unsigned char *buf, int size) 258 { 259 struct spi_flash *spi; 260 int ret; 261 262 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 263 if (spi == NULL) { 264 printf("%s: spi_flash probe error.\n", __func__); 265 return 1; 266 } 267 268 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf); 269 if (ret) { 270 printf("%s: spi_flash read error.\n", __func__); 271 spi_flash_free(spi); 272 return 1; 273 } 274 spi_flash_free(spi); 275 276 return 0; 277 } 278 279 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) 280 { 281 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)], 282 SH7757LCR_ETHERNET_MAC_SIZE); 283 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ 284 285 return 0; 286 } 287 288 static void init_ethernet_mac(void) 289 { 290 char mac_string[64]; 291 char env_string[64]; 292 int i; 293 unsigned char *buf; 294 295 buf = malloc(256); 296 if (!buf) { 297 printf("%s: malloc error.\n", __func__); 298 return; 299 } 300 get_sh_eth_mac_raw(buf, 256); 301 302 /* Fast Ethernet */ 303 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) { 304 get_sh_eth_mac(i, mac_string, buf); 305 if (i == 0) 306 setenv("ethaddr", mac_string); 307 else { 308 sprintf(env_string, "eth%daddr", i); 309 setenv(env_string, mac_string); 310 } 311 312 set_mac_to_sh_eth_register(i, mac_string); 313 } 314 315 /* Gigabit Ethernet */ 316 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) { 317 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf); 318 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH); 319 setenv(env_string, mac_string); 320 321 set_mac_to_sh_giga_eth_register(i, mac_string); 322 } 323 324 free(buf); 325 } 326 327 static void init_pcie(void) 328 { 329 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; 330 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE; 331 332 writel(0x00000ff2, &pcie_setup->ladmsk0); 333 writel(0x00000001, &pcie_setup->barmap); 334 writel(0xffcaa000, &pcie_setup->lad0); 335 writel(0x00030000, &pcie_sysbus->endictl0); 336 writel(0x00000003, &pcie_sysbus->endictl1); 337 writel(0x00000004, &pcie_setup->pbictl2); 338 } 339 340 static void finish_spiboot(void) 341 { 342 struct gctrl_regs *gctrl = GCTRL_BASE; 343 /* 344 * SH7757 B0 does not use LBSC. 345 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0. 346 * This setting is not cleared by manual reset, So we have to set it 347 * to 0. 348 */ 349 writel(0x00000000, &gctrl->spibootcan); 350 } 351 352 int board_late_init(void) 353 { 354 init_ethernet_mac(); 355 init_pcie_bridge(); 356 init_pcie(); 357 finish_spiboot(); 358 359 return 0; 360 } 361 362 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 363 { 364 struct gctrl_regs *gctrl = GCTRL_BASE; 365 unsigned long graofst; 366 367 writel(0xfedcba98, &gctrl->wprotect); 368 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; 369 writel(graofst | 0xa0000f00, &gctrl->gracr3); 370 371 return 0; 372 } 373 374 U_BOOT_CMD( 375 sh_g200, 1, 1, do_sh_g200, 376 "enable sh-g200", 377 "enable SH-G200 bus (disable PCIe-G200)" 378 ); 379 380 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 381 { 382 int i, ret; 383 char mac_string[256]; 384 struct spi_flash *spi; 385 unsigned char *buf; 386 387 if (argc != 5) { 388 buf = malloc(256); 389 if (!buf) { 390 printf("%s: malloc error.\n", __func__); 391 return 1; 392 } 393 394 get_sh_eth_mac_raw(buf, 256); 395 396 /* print current MAC address */ 397 for (i = 0; i < 4; i++) { 398 get_sh_eth_mac(i, mac_string, buf); 399 if (i < 2) 400 printf(" ETHERC ch%d = %s\n", i, mac_string); 401 else 402 printf("GETHERC ch%d = %s\n", i-2, mac_string); 403 } 404 free(buf); 405 return 0; 406 } 407 408 /* new setting */ 409 memset(mac_string, 0xff, sizeof(mac_string)); 410 sprintf(mac_string, "%s\t%s\t%s\t%s", 411 argv[1], argv[2], argv[3], argv[4]); 412 413 /* write MAC data to SPI rom */ 414 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 415 if (!spi) { 416 printf("%s: spi_flash probe error.\n", __func__); 417 return 1; 418 } 419 420 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, 421 SH7757LCR_SPI_SECTOR_SIZE); 422 if (ret) { 423 printf("%s: spi_flash erase error.\n", __func__); 424 return 1; 425 } 426 427 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, 428 sizeof(mac_string), mac_string); 429 if (ret) { 430 printf("%s: spi_flash write error.\n", __func__); 431 spi_flash_free(spi); 432 return 1; 433 } 434 spi_flash_free(spi); 435 436 puts("The writing of the MAC address to SPI ROM was completed.\n"); 437 438 return 0; 439 } 440 441 U_BOOT_CMD( 442 write_mac, 5, 1, do_write_mac, 443 "write MAC address for ETHERC/GETHERC", 444 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" 445 ); 446