1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2011  Renesas Solutions Corp.
4 */
5
6#include <config.h>
7#include <asm/processor.h>
8#include <asm/macro.h>
9
10.macro	or32, addr, data
11	mov.l \addr, r1
12	mov.l \data, r0
13	mov.l @r1, r2
14	or    r2, r0
15	mov.l r0, @r1
16.endm
17
18.macro	wait_DBCMD
19	mov.l	DBWAIT_A, r0
20	mov.l	@r0, r1
21.endm
22
23	.global lowlevel_init
24	.section	.spiboot1.text
25	.align  2
26
27lowlevel_init:
28
29	/*------- GPIO -------*/
30	write8 PGDR_A,	PGDR_D	/* eMMC power off */
31
32	write16 PACR_A,	PACR_D
33	write16 PBCR_A,	PBCR_D
34	write16 PCCR_A,	PCCR_D
35	write16 PDCR_A,	PDCR_D
36	write16 PECR_A,	PECR_D
37	write16 PFCR_A,	PFCR_D
38	write16 PGCR_A,	PGCR_D
39	write16 PHCR_A,	PHCR_D
40	write16 PICR_A,	PICR_D
41	write16 PJCR_A,	PJCR_D
42	write16 PKCR_A,	PKCR_D
43	write16 PLCR_A,	PLCR_D
44	write16 PMCR_A,	PMCR_D
45	write16 PNCR_A,	PNCR_D
46	write16 POCR_A,	POCR_D
47	write16 PQCR_A,	PQCR_D
48	write16 PRCR_A,	PRCR_D
49	write16 PSCR_A,	PSCR_D
50	write16 PTCR_A,	PTCR_D
51	write16 PUCR_A,	PUCR_D
52	write16 PVCR_A,	PVCR_D
53	write16 PWCR_A,	PWCR_D
54	write16 PXCR_A,	PXCR_D
55	write16 PYCR_A,	PYCR_D
56	write16 PZCR_A,	PZCR_D
57	write16 PSEL0_A, PSEL0_D
58	write16 PSEL1_A, PSEL1_D
59	write16 PSEL2_A, PSEL2_D
60	write16 PSEL3_A, PSEL3_D
61	write16 PSEL4_A, PSEL4_D
62	write16 PSEL5_A, PSEL5_D
63	write16 PSEL6_A, PSEL6_D
64	write16 PSEL7_A, PSEL7_D
65	write16 PSEL8_A, PSEL8_D
66
67	bra	exit_gpio
68	nop
69
70	.align	4
71
72/*------- GPIO -------*/
73PGDR_A:		.long	0xffec0040
74PACR_A:		.long	0xffec0000
75PBCR_A:		.long	0xffec0002
76PCCR_A:		.long	0xffec0004
77PDCR_A:		.long	0xffec0006
78PECR_A:		.long	0xffec0008
79PFCR_A:		.long	0xffec000a
80PGCR_A:		.long	0xffec000c
81PHCR_A:		.long	0xffec000e
82PICR_A:		.long	0xffec0010
83PJCR_A:		.long	0xffec0012
84PKCR_A:		.long	0xffec0014
85PLCR_A:		.long	0xffec0016
86PMCR_A:		.long	0xffec0018
87PNCR_A:		.long	0xffec001a
88POCR_A:		.long	0xffec001c
89PQCR_A:		.long	0xffec0020
90PRCR_A:		.long	0xffec0022
91PSCR_A:		.long	0xffec0024
92PTCR_A:		.long	0xffec0026
93PUCR_A:		.long	0xffec0028
94PVCR_A:		.long	0xffec002a
95PWCR_A:		.long	0xffec002c
96PXCR_A:		.long	0xffec002e
97PYCR_A:		.long	0xffec0030
98PZCR_A:		.long	0xffec0032
99PSEL0_A:	.long	0xffec0070
100PSEL1_A:	.long	0xffec0072
101PSEL2_A:	.long	0xffec0074
102PSEL3_A:	.long	0xffec0076
103PSEL4_A:	.long	0xffec0078
104PSEL5_A:	.long	0xffec007a
105PSEL6_A:	.long	0xffec007c
106PSEL7_A:	.long	0xffec0082
107PSEL8_A:	.long	0xffec0084
108
109PGDR_D:		.long	0x80
110PACR_D:		.long	0x0000
111PBCR_D:		.long	0x0001
112PCCR_D:		.long	0x0000
113PDCR_D:		.long	0x0000
114PECR_D:		.long	0x0000
115PFCR_D:		.long	0x0000
116PGCR_D:		.long	0x0000
117PHCR_D:		.long	0x0000
118PICR_D:		.long	0x0000
119PJCR_D:		.long	0x0000
120PKCR_D:		.long	0x0003
121PLCR_D:		.long	0x0000
122PMCR_D:		.long	0x0000
123PNCR_D:		.long	0x0000
124POCR_D:		.long	0x0000
125PQCR_D:		.long	0xc000
126PRCR_D:		.long	0x0000
127PSCR_D:		.long	0x0000
128PTCR_D:		.long	0x0000
129#if defined(CONFIG_SH7757_OFFSET_SPI)
130PUCR_D:		.long	0x0055
131#else
132PUCR_D:		.long	0x0000
133#endif
134PVCR_D:		.long	0x0000
135PWCR_D:		.long	0x0000
136PXCR_D:		.long	0x0000
137PYCR_D:		.long	0x0000
138PZCR_D:		.long	0x0000
139PSEL0_D:	.long	0xfe00
140PSEL1_D:	.long	0x0000
141PSEL2_D:	.long	0x3000
142PSEL3_D:	.long	0xff00
143PSEL4_D:	.long	0x771f
144PSEL5_D:	.long	0x0ffc
145PSEL6_D:	.long	0x00ff
146PSEL7_D:	.long	0xfc00
147PSEL8_D:	.long	0x0000
148
149	.align	2
150
151exit_gpio:
152	mov	#0, r14
153	mova	2f, r0
154	mov.l	PC_MASK, r1
155	tst	r0, r1
156	bf	2f
157
158	bra	exit_pmb
159	nop
160
161	.align	2
162
163/* If CPU runs on SDRAM, PC is 0x8???????. */
164PC_MASK:	.long	0x20000000
165
1662:
167	mov	#1, r14
168
169	mov.l	EXPEVT_A, r0
170	mov.l	@r0, r0
171	mov.l	EXPEVT_POWER_ON_RESET, r1
172	cmp/eq	r0, r1
173	bt	1f
174
175	/*
176	 * If EXPEVT value is manual reset or tlb multipul-hit,
177	 * initialization of DDR3IF is not necessary.
178	 */
179	bra	exit_ddr
180	nop
181
1821:
183	/* For Core Reset */
184	mov.l	DBACEN_A, r0
185	mov.l	@r0, r0
186	cmp/eq	#0, r0
187	bt	3f
188
189	/*
190	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
191	 * initialization of DDR3-SDRAM.
192	 */
193	bra	exit_ddr
194	nop
195
1963:
197	/*------- DDR3IF -------*/
198	/* oscillation stabilization time */
199	wait_timer	WAIT_OSC_TIME
200
201	/* step 3 */
202	write32 DBCMD_A, DBCMD_RSTL_VAL
203	wait_timer	WAIT_30US
204
205	/* step 4 */
206	write32 DBCMD_A, DBCMD_PDEN_VAL
207
208	/* step 5 */
209	write32 DBKIND_A, DBKIND_D
210
211	/* step 6 */
212	write32 DBCONF_A, DBCONF_D
213	write32 DBTR0_A, DBTR0_D
214	write32 DBTR1_A, DBTR1_D
215	write32 DBTR2_A, DBTR2_D
216	write32 DBTR3_A, DBTR3_D
217	write32 DBTR4_A, DBTR4_D
218	write32 DBTR5_A, DBTR5_D
219	write32 DBTR6_A, DBTR6_D
220	write32 DBTR7_A, DBTR7_D
221	write32 DBTR8_A, DBTR8_D
222	write32 DBTR9_A, DBTR9_D
223	write32 DBTR10_A, DBTR10_D
224	write32 DBTR11_A, DBTR11_D
225	write32 DBTR12_A, DBTR12_D
226	write32 DBTR13_A, DBTR13_D
227	write32 DBTR14_A, DBTR14_D
228	write32 DBTR15_A, DBTR15_D
229	write32 DBTR16_A, DBTR16_D
230	write32 DBTR17_A, DBTR17_D
231	write32 DBTR18_A, DBTR18_D
232	write32 DBTR19_A, DBTR19_D
233	write32 DBRNK0_A, DBRNK0_D
234
235	/* step 7 */
236	write32 DBPDCNT3_A, DBPDCNT3_D
237
238	/* step 8 */
239	write32 DBPDCNT1_A, DBPDCNT1_D
240	write32 DBPDCNT2_A, DBPDCNT2_D
241	write32 DBPDLCK_A, DBPDLCK_D
242	write32 DBPDRGA_A, DBPDRGA_D
243	write32 DBPDRGD_A, DBPDRGD_D
244
245	/* step 9 */
246	wait_timer	WAIT_30US
247
248	/* step 10 */
249	write32 DBPDCNT0_A, DBPDCNT0_D
250
251	/* step 11 */
252	wait_timer	WAIT_30US
253	wait_timer	WAIT_30US
254
255	/* step 12 */
256	write32 DBCMD_A, DBCMD_WAIT_VAL
257	wait_DBCMD
258
259	/* step 13 */
260	write32 DBCMD_A, DBCMD_RSTH_VAL
261	wait_DBCMD
262
263	/* step 14 */
264	write32 DBCMD_A, DBCMD_WAIT_VAL
265	write32 DBCMD_A, DBCMD_WAIT_VAL
266	write32 DBCMD_A, DBCMD_WAIT_VAL
267	write32 DBCMD_A, DBCMD_WAIT_VAL
268
269	/* step 15 */
270	write32 DBCMD_A, DBCMD_PDXT_VAL
271
272	/* step 16 */
273	write32 DBCMD_A, DBCMD_MRS2_VAL
274
275	/* step 17 */
276	write32 DBCMD_A, DBCMD_MRS3_VAL
277
278	/* step 18 */
279	write32 DBCMD_A, DBCMD_MRS1_VAL
280
281	/* step 19 */
282	write32 DBCMD_A, DBCMD_MRS0_VAL
283
284	/* step 20 */
285	write32 DBCMD_A, DBCMD_ZQCL_VAL
286
287	write32 DBCMD_A, DBCMD_REF_VAL
288	write32 DBCMD_A, DBCMD_REF_VAL
289	wait_DBCMD
290
291	/* step 21 */
292	write32 DBADJ0_A, DBADJ0_D
293	write32 DBADJ1_A, DBADJ1_D
294	write32 DBADJ2_A, DBADJ2_D
295
296	/* step 22 */
297	write32 DBRFCNF0_A, DBRFCNF0_D
298	write32 DBRFCNF1_A, DBRFCNF1_D
299	write32 DBRFCNF2_A, DBRFCNF2_D
300
301	/* step 23 */
302	write32 DBCALCNF_A, DBCALCNF_D
303
304	/* step 24 */
305	write32 DBRFEN_A, DBRFEN_D
306	write32 DBCMD_A, DBCMD_SRXT_VAL
307
308	/* step 25 */
309	write32 DBACEN_A, DBACEN_D
310
311	/* step 26 */
312	wait_DBCMD
313
314#if defined(CONFIG_SH7757LCR_DDR_ECC)
315	/* enable DDR-ECC */
316	write32 ECD_ECDEN_A, ECD_ECDEN_D
317	write32 ECD_INTSR_A, ECD_INTSR_D
318	write32 ECD_SPACER_A, ECD_SPACER_D
319	write32 ECD_MCR_A, ECD_MCR_D
320#endif
321	bra	exit_ddr
322	nop
323
324	.align 4
325
326EXPEVT_A:		.long	0xff000024
327EXPEVT_POWER_ON_RESET:	.long	0x00000000
328
329/*------- DDR3IF -------*/
330DBCMD_A:	.long	0xfe800018
331DBKIND_A:	.long	0xfe800020
332DBCONF_A:	.long	0xfe800024
333DBTR0_A:	.long	0xfe800040
334DBTR1_A:	.long	0xfe800044
335DBTR2_A:	.long	0xfe800048
336DBTR3_A:	.long	0xfe800050
337DBTR4_A:	.long	0xfe800054
338DBTR5_A:	.long	0xfe800058
339DBTR6_A:	.long	0xfe80005c
340DBTR7_A:	.long	0xfe800060
341DBTR8_A:	.long	0xfe800064
342DBTR9_A:	.long	0xfe800068
343DBTR10_A:	.long	0xfe80006c
344DBTR11_A:	.long	0xfe800070
345DBTR12_A:	.long	0xfe800074
346DBTR13_A:	.long	0xfe800078
347DBTR14_A:	.long	0xfe80007c
348DBTR15_A:	.long	0xfe800080
349DBTR16_A:	.long	0xfe800084
350DBTR17_A:	.long	0xfe800088
351DBTR18_A:	.long	0xfe80008c
352DBTR19_A:	.long	0xfe800090
353DBRNK0_A:	.long	0xfe800100
354DBPDCNT0_A:	.long	0xfe800200
355DBPDCNT1_A:	.long	0xfe800204
356DBPDCNT2_A:	.long	0xfe800208
357DBPDCNT3_A:	.long	0xfe80020c
358DBPDLCK_A:	.long	0xfe800280
359DBPDRGA_A:	.long	0xfe800290
360DBPDRGD_A:	.long	0xfe8002a0
361DBADJ0_A:	.long	0xfe8000c0
362DBADJ1_A:	.long	0xfe8000c4
363DBADJ2_A:	.long	0xfe8000c8
364DBRFCNF0_A:	.long	0xfe8000e0
365DBRFCNF1_A:	.long	0xfe8000e4
366DBRFCNF2_A:	.long	0xfe8000e8
367DBCALCNF_A:	.long	0xfe8000f4
368DBRFEN_A:	.long	0xfe800014
369DBACEN_A:	.long	0xfe800010
370DBWAIT_A:	.long	0xfe80001c
371
372WAIT_OSC_TIME:	.long	6000
373WAIT_30US:	.long	13333
374
375DBCMD_RSTL_VAL:	.long	0x20000000
376DBCMD_PDEN_VAL:	.long	0x1000d73c
377DBCMD_WAIT_VAL:	.long	0x0000d73c
378DBCMD_RSTH_VAL:	.long	0x2100d73c
379DBCMD_PDXT_VAL:	.long	0x110000c8
380DBCMD_MRS0_VAL:	.long	0x28000930
381DBCMD_MRS1_VAL:	.long	0x29000004
382DBCMD_MRS2_VAL:	.long	0x2a000008
383DBCMD_MRS3_VAL:	.long	0x2b000000
384DBCMD_ZQCL_VAL:	.long	0x03000200
385DBCMD_REF_VAL:	.long	0x0c000000
386DBCMD_SRXT_VAL:	.long	0x19000000
387DBKIND_D:	.long	0x00000007
388DBCONF_D:	.long	0x0f030a01
389DBTR0_D:	.long	0x00000007
390DBTR1_D:	.long	0x00000006
391DBTR2_D:	.long	0x00000000
392DBTR3_D:	.long	0x00000007
393DBTR4_D:	.long	0x00070007
394DBTR5_D:	.long	0x0000001b
395DBTR6_D:	.long	0x00000014
396DBTR7_D:	.long	0x00000005
397DBTR8_D:	.long	0x00000015
398DBTR9_D:	.long	0x00000006
399DBTR10_D:	.long	0x00000008
400DBTR11_D:	.long	0x00000007
401DBTR12_D:	.long	0x0000000e
402DBTR13_D:	.long	0x00000056
403DBTR14_D:	.long	0x00000006
404DBTR15_D:	.long	0x00000004
405DBTR16_D:	.long	0x00150002
406DBTR17_D:	.long	0x000c0017
407DBTR18_D:	.long	0x00000200
408DBTR19_D:	.long	0x00000040
409DBRNK0_D:	.long	0x00000001
410DBPDCNT0_D:	.long	0x00000001
411DBPDCNT1_D:	.long	0x00000001
412DBPDCNT2_D:	.long	0x00000000
413DBPDCNT3_D:	.long	0x00004010
414DBPDLCK_D:	.long	0x0000a55a
415DBPDRGA_D:	.long	0x00000028
416DBPDRGD_D:	.long	0x00017100
417
418DBADJ0_D:	.long	0x00000000
419DBADJ1_D:	.long	0x00000000
420DBADJ2_D:	.long	0x18061806
421DBRFCNF0_D:	.long	0x000001ff
422DBRFCNF1_D:	.long	0x08001000
423DBRFCNF2_D:	.long	0x00000000
424DBCALCNF_D:	.long	0x0000ffff
425DBRFEN_D:	.long	0x00000001
426DBACEN_D:	.long	0x00000001
427
428/*------- DDR-ECC -------*/
429ECD_ECDEN_A:	.long	0xffc1012c
430ECD_ECDEN_D:	.long	0x00000001
431ECD_INTSR_A:	.long	0xfe900024
432ECD_INTSR_D:	.long	0xffffffff
433ECD_SPACER_A:	.long	0xfe900018
434ECD_SPACER_D:	.long	SH7757LCR_SDRAM_ECC_SETTING
435ECD_MCR_A:	.long	0xfe900010
436ECD_MCR_D:	.long	0x00000001
437
438	.align 2
439exit_ddr:
440
441#if defined(CONFIG_SH_32BIT)
442	/*------- set PMB -------*/
443	write32	PASCR_A,	PASCR_29BIT_D
444	write32	MMUCR_A,	MMUCR_D
445
446	/*****************************************************************
447	 * ent	virt		phys		v	sz	c	wt
448	 * 0	0xa0000000	0x00000000	1	128M	0	1
449	 * 1	0xa8000000	0x48000000	1	128M	0	1
450	 * 5	0x88000000	0x48000000	1	128M	1	1
451	 */
452	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
453	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
454	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
455	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
456	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
457	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
458
459	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
460	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
461	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
462	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
463	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
464	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
465	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
466	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
467	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
468	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
469	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
470	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
471	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
472
473	write32	PASCR_A,	PASCR_INIT
474	mov.l	DUMMY_ADDR, r0
475	icbi	@r0
476#endif	/* if defined(CONFIG_SH_32BIT) */
477
478exit_pmb:
479	/* CPU is running on ILRAM? */
480	mov	r14, r0
481	tst	#1, r0
482	bt	1f
483
484	mov.l	_bss_start, r15
485	mov.l	_spiboot_main, r0
486100:	bsrf	r0
487	nop
488
489	.align	2
490_spiboot_main:	.long	(spiboot_main - (100b + 4))
491_bss_start:	.long	bss_start
492
4931:
494
495	write32	CCR_A,	CCR_D
496
497	rts
498	 nop
499
500	.align 4
501
502#if defined(CONFIG_SH_32BIT)
503/*------- set PMB -------*/
504PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
505PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
506PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
507PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
508PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
509PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
510PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
511PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
512PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
513PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
514PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
515PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
516PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
517PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
518PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
519PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
520
521PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
522PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
523PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
524PMB_ADDR_NOT_USE_D:	.long	0x00000000
525
526PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
527PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
528PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
529
530/*						ppn   ub v s1 s0  c  wt */
531PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
532PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
533PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
534
535PASCR_A:		.long	0xff000070
536DUMMY_ADDR:		.long	0xa0000000
537PASCR_29BIT_D:		.long	0x00000000
538PASCR_INIT:		.long	0x80000080
539MMUCR_A:		.long	0xff000010
540MMUCR_D:		.long	0x00000004	/* clear ITLB */
541#endif	/* CONFIG_SH_32BIT */
542
543CCR_A:		.long	CCR
544CCR_D:		.long	CCR_CACHE_INIT
545