1/*
2 * Copyright (C) 2011  Renesas Solutions Corp.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include <config.h>
8#include <version.h>
9#include <asm/processor.h>
10#include <asm/macro.h>
11
12.macro	or32, addr, data
13	mov.l \addr, r1
14	mov.l \data, r0
15	mov.l @r1, r2
16	or    r2, r0
17	mov.l r0, @r1
18.endm
19
20.macro	wait_DBCMD
21	mov.l	DBWAIT_A, r0
22	mov.l	@r0, r1
23.endm
24
25	.global lowlevel_init
26	.section	.spiboot1.text
27	.align  2
28
29lowlevel_init:
30
31	/*------- GPIO -------*/
32	write8 PGDR_A,	PGDR_D	/* eMMC power off */
33
34	write16 PACR_A,	PACR_D
35	write16 PBCR_A,	PBCR_D
36	write16 PCCR_A,	PCCR_D
37	write16 PDCR_A,	PDCR_D
38	write16 PECR_A,	PECR_D
39	write16 PFCR_A,	PFCR_D
40	write16 PGCR_A,	PGCR_D
41	write16 PHCR_A,	PHCR_D
42	write16 PICR_A,	PICR_D
43	write16 PJCR_A,	PJCR_D
44	write16 PKCR_A,	PKCR_D
45	write16 PLCR_A,	PLCR_D
46	write16 PMCR_A,	PMCR_D
47	write16 PNCR_A,	PNCR_D
48	write16 POCR_A,	POCR_D
49	write16 PQCR_A,	PQCR_D
50	write16 PRCR_A,	PRCR_D
51	write16 PSCR_A,	PSCR_D
52	write16 PTCR_A,	PTCR_D
53	write16 PUCR_A,	PUCR_D
54	write16 PVCR_A,	PVCR_D
55	write16 PWCR_A,	PWCR_D
56	write16 PXCR_A,	PXCR_D
57	write16 PYCR_A,	PYCR_D
58	write16 PZCR_A,	PZCR_D
59	write16 PSEL0_A, PSEL0_D
60	write16 PSEL1_A, PSEL1_D
61	write16 PSEL2_A, PSEL2_D
62	write16 PSEL3_A, PSEL3_D
63	write16 PSEL4_A, PSEL4_D
64	write16 PSEL5_A, PSEL5_D
65	write16 PSEL6_A, PSEL6_D
66	write16 PSEL7_A, PSEL7_D
67	write16 PSEL8_A, PSEL8_D
68
69	bra	exit_gpio
70	nop
71
72	.align	4
73
74/*------- GPIO -------*/
75PGDR_A:		.long	0xffec0040
76PACR_A:		.long	0xffec0000
77PBCR_A:		.long	0xffec0002
78PCCR_A:		.long	0xffec0004
79PDCR_A:		.long	0xffec0006
80PECR_A:		.long	0xffec0008
81PFCR_A:		.long	0xffec000a
82PGCR_A:		.long	0xffec000c
83PHCR_A:		.long	0xffec000e
84PICR_A:		.long	0xffec0010
85PJCR_A:		.long	0xffec0012
86PKCR_A:		.long	0xffec0014
87PLCR_A:		.long	0xffec0016
88PMCR_A:		.long	0xffec0018
89PNCR_A:		.long	0xffec001a
90POCR_A:		.long	0xffec001c
91PQCR_A:		.long	0xffec0020
92PRCR_A:		.long	0xffec0022
93PSCR_A:		.long	0xffec0024
94PTCR_A:		.long	0xffec0026
95PUCR_A:		.long	0xffec0028
96PVCR_A:		.long	0xffec002a
97PWCR_A:		.long	0xffec002c
98PXCR_A:		.long	0xffec002e
99PYCR_A:		.long	0xffec0030
100PZCR_A:		.long	0xffec0032
101PSEL0_A:	.long	0xffec0070
102PSEL1_A:	.long	0xffec0072
103PSEL2_A:	.long	0xffec0074
104PSEL3_A:	.long	0xffec0076
105PSEL4_A:	.long	0xffec0078
106PSEL5_A:	.long	0xffec007a
107PSEL6_A:	.long	0xffec007c
108PSEL7_A:	.long	0xffec0082
109PSEL8_A:	.long	0xffec0084
110
111PGDR_D:		.long	0x80
112PACR_D:		.long	0x0000
113PBCR_D:		.long	0x0001
114PCCR_D:		.long	0x0000
115PDCR_D:		.long	0x0000
116PECR_D:		.long	0x0000
117PFCR_D:		.long	0x0000
118PGCR_D:		.long	0x0000
119PHCR_D:		.long	0x0000
120PICR_D:		.long	0x0000
121PJCR_D:		.long	0x0000
122PKCR_D:		.long	0x0003
123PLCR_D:		.long	0x0000
124PMCR_D:		.long	0x0000
125PNCR_D:		.long	0x0000
126POCR_D:		.long	0x0000
127PQCR_D:		.long	0xc000
128PRCR_D:		.long	0x0000
129PSCR_D:		.long	0x0000
130PTCR_D:		.long	0x0000
131#if defined(CONFIG_SH7757_OFFSET_SPI)
132PUCR_D:		.long	0x0055
133#else
134PUCR_D:		.long	0x0000
135#endif
136PVCR_D:		.long	0x0000
137PWCR_D:		.long	0x0000
138PXCR_D:		.long	0x0000
139PYCR_D:		.long	0x0000
140PZCR_D:		.long	0x0000
141PSEL0_D:	.long	0xfe00
142PSEL1_D:	.long	0x0000
143PSEL2_D:	.long	0x3000
144PSEL3_D:	.long	0xff00
145PSEL4_D:	.long	0x771f
146PSEL5_D:	.long	0x0ffc
147PSEL6_D:	.long	0x00ff
148PSEL7_D:	.long	0xfc00
149PSEL8_D:	.long	0x0000
150
151	.align	2
152
153exit_gpio:
154	mov	#0, r14
155	mova	2f, r0
156	mov.l	PC_MASK, r1
157	tst	r0, r1
158	bf	2f
159
160	bra	exit_pmb
161	nop
162
163	.align	2
164
165/* If CPU runs on SDRAM, PC is 0x8???????. */
166PC_MASK:	.long	0x20000000
167
1682:
169	mov	#1, r14
170
171	mov.l	EXPEVT_A, r0
172	mov.l	@r0, r0
173	mov.l	EXPEVT_POWER_ON_RESET, r1
174	cmp/eq	r0, r1
175	bt	1f
176
177	/*
178	 * If EXPEVT value is manual reset or tlb multipul-hit,
179	 * initialization of DDR3IF is not necessary.
180	 */
181	bra	exit_ddr
182	nop
183
1841:
185	/* For Core Reset */
186	mov.l	DBACEN_A, r0
187	mov.l	@r0, r0
188	cmp/eq	#0, r0
189	bt	3f
190
191	/*
192	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
193	 * initialization of DDR3-SDRAM.
194	 */
195	bra	exit_ddr
196	nop
197
1983:
199	/*------- DDR3IF -------*/
200	/* oscillation stabilization time */
201	wait_timer	WAIT_OSC_TIME
202
203	/* step 3 */
204	write32 DBCMD_A, DBCMD_RSTL_VAL
205	wait_timer	WAIT_30US
206
207	/* step 4 */
208	write32 DBCMD_A, DBCMD_PDEN_VAL
209
210	/* step 5 */
211	write32 DBKIND_A, DBKIND_D
212
213	/* step 6 */
214	write32 DBCONF_A, DBCONF_D
215	write32 DBTR0_A, DBTR0_D
216	write32 DBTR1_A, DBTR1_D
217	write32 DBTR2_A, DBTR2_D
218	write32 DBTR3_A, DBTR3_D
219	write32 DBTR4_A, DBTR4_D
220	write32 DBTR5_A, DBTR5_D
221	write32 DBTR6_A, DBTR6_D
222	write32 DBTR7_A, DBTR7_D
223	write32 DBTR8_A, DBTR8_D
224	write32 DBTR9_A, DBTR9_D
225	write32 DBTR10_A, DBTR10_D
226	write32 DBTR11_A, DBTR11_D
227	write32 DBTR12_A, DBTR12_D
228	write32 DBTR13_A, DBTR13_D
229	write32 DBTR14_A, DBTR14_D
230	write32 DBTR15_A, DBTR15_D
231	write32 DBTR16_A, DBTR16_D
232	write32 DBTR17_A, DBTR17_D
233	write32 DBTR18_A, DBTR18_D
234	write32 DBTR19_A, DBTR19_D
235	write32 DBRNK0_A, DBRNK0_D
236
237	/* step 7 */
238	write32 DBPDCNT3_A, DBPDCNT3_D
239
240	/* step 8 */
241	write32 DBPDCNT1_A, DBPDCNT1_D
242	write32 DBPDCNT2_A, DBPDCNT2_D
243	write32 DBPDLCK_A, DBPDLCK_D
244	write32 DBPDRGA_A, DBPDRGA_D
245	write32 DBPDRGD_A, DBPDRGD_D
246
247	/* step 9 */
248	wait_timer	WAIT_30US
249
250	/* step 10 */
251	write32 DBPDCNT0_A, DBPDCNT0_D
252
253	/* step 11 */
254	wait_timer	WAIT_30US
255	wait_timer	WAIT_30US
256
257	/* step 12 */
258	write32 DBCMD_A, DBCMD_WAIT_VAL
259	wait_DBCMD
260
261	/* step 13 */
262	write32 DBCMD_A, DBCMD_RSTH_VAL
263	wait_DBCMD
264
265	/* step 14 */
266	write32 DBCMD_A, DBCMD_WAIT_VAL
267	write32 DBCMD_A, DBCMD_WAIT_VAL
268	write32 DBCMD_A, DBCMD_WAIT_VAL
269	write32 DBCMD_A, DBCMD_WAIT_VAL
270
271	/* step 15 */
272	write32 DBCMD_A, DBCMD_PDXT_VAL
273
274	/* step 16 */
275	write32 DBCMD_A, DBCMD_MRS2_VAL
276
277	/* step 17 */
278	write32 DBCMD_A, DBCMD_MRS3_VAL
279
280	/* step 18 */
281	write32 DBCMD_A, DBCMD_MRS1_VAL
282
283	/* step 19 */
284	write32 DBCMD_A, DBCMD_MRS0_VAL
285
286	/* step 20 */
287	write32 DBCMD_A, DBCMD_ZQCL_VAL
288
289	write32 DBCMD_A, DBCMD_REF_VAL
290	write32 DBCMD_A, DBCMD_REF_VAL
291	wait_DBCMD
292
293	/* step 21 */
294	write32 DBADJ0_A, DBADJ0_D
295	write32 DBADJ1_A, DBADJ1_D
296	write32 DBADJ2_A, DBADJ2_D
297
298	/* step 22 */
299	write32 DBRFCNF0_A, DBRFCNF0_D
300	write32 DBRFCNF1_A, DBRFCNF1_D
301	write32 DBRFCNF2_A, DBRFCNF2_D
302
303	/* step 23 */
304	write32 DBCALCNF_A, DBCALCNF_D
305
306	/* step 24 */
307	write32 DBRFEN_A, DBRFEN_D
308	write32 DBCMD_A, DBCMD_SRXT_VAL
309
310	/* step 25 */
311	write32 DBACEN_A, DBACEN_D
312
313	/* step 26 */
314	wait_DBCMD
315
316#if defined(CONFIG_SH7757LCR_DDR_ECC)
317	/* enable DDR-ECC */
318	write32 ECD_ECDEN_A, ECD_ECDEN_D
319	write32 ECD_INTSR_A, ECD_INTSR_D
320	write32 ECD_SPACER_A, ECD_SPACER_D
321	write32 ECD_MCR_A, ECD_MCR_D
322#endif
323	bra	exit_ddr
324	nop
325
326	.align 4
327
328EXPEVT_A:		.long	0xff000024
329EXPEVT_POWER_ON_RESET:	.long	0x00000000
330
331/*------- DDR3IF -------*/
332DBCMD_A:	.long	0xfe800018
333DBKIND_A:	.long	0xfe800020
334DBCONF_A:	.long	0xfe800024
335DBTR0_A:	.long	0xfe800040
336DBTR1_A:	.long	0xfe800044
337DBTR2_A:	.long	0xfe800048
338DBTR3_A:	.long	0xfe800050
339DBTR4_A:	.long	0xfe800054
340DBTR5_A:	.long	0xfe800058
341DBTR6_A:	.long	0xfe80005c
342DBTR7_A:	.long	0xfe800060
343DBTR8_A:	.long	0xfe800064
344DBTR9_A:	.long	0xfe800068
345DBTR10_A:	.long	0xfe80006c
346DBTR11_A:	.long	0xfe800070
347DBTR12_A:	.long	0xfe800074
348DBTR13_A:	.long	0xfe800078
349DBTR14_A:	.long	0xfe80007c
350DBTR15_A:	.long	0xfe800080
351DBTR16_A:	.long	0xfe800084
352DBTR17_A:	.long	0xfe800088
353DBTR18_A:	.long	0xfe80008c
354DBTR19_A:	.long	0xfe800090
355DBRNK0_A:	.long	0xfe800100
356DBPDCNT0_A:	.long	0xfe800200
357DBPDCNT1_A:	.long	0xfe800204
358DBPDCNT2_A:	.long	0xfe800208
359DBPDCNT3_A:	.long	0xfe80020c
360DBPDLCK_A:	.long	0xfe800280
361DBPDRGA_A:	.long	0xfe800290
362DBPDRGD_A:	.long	0xfe8002a0
363DBADJ0_A:	.long	0xfe8000c0
364DBADJ1_A:	.long	0xfe8000c4
365DBADJ2_A:	.long	0xfe8000c8
366DBRFCNF0_A:	.long	0xfe8000e0
367DBRFCNF1_A:	.long	0xfe8000e4
368DBRFCNF2_A:	.long	0xfe8000e8
369DBCALCNF_A:	.long	0xfe8000f4
370DBRFEN_A:	.long	0xfe800014
371DBACEN_A:	.long	0xfe800010
372DBWAIT_A:	.long	0xfe80001c
373
374WAIT_OSC_TIME:	.long	6000
375WAIT_30US:	.long	13333
376
377DBCMD_RSTL_VAL:	.long	0x20000000
378DBCMD_PDEN_VAL:	.long	0x1000d73c
379DBCMD_WAIT_VAL:	.long	0x0000d73c
380DBCMD_RSTH_VAL:	.long	0x2100d73c
381DBCMD_PDXT_VAL:	.long	0x110000c8
382DBCMD_MRS0_VAL:	.long	0x28000930
383DBCMD_MRS1_VAL:	.long	0x29000004
384DBCMD_MRS2_VAL:	.long	0x2a000008
385DBCMD_MRS3_VAL:	.long	0x2b000000
386DBCMD_ZQCL_VAL:	.long	0x03000200
387DBCMD_REF_VAL:	.long	0x0c000000
388DBCMD_SRXT_VAL:	.long	0x19000000
389DBKIND_D:	.long	0x00000007
390DBCONF_D:	.long	0x0f030a01
391DBTR0_D:	.long	0x00000007
392DBTR1_D:	.long	0x00000006
393DBTR2_D:	.long	0x00000000
394DBTR3_D:	.long	0x00000007
395DBTR4_D:	.long	0x00070007
396DBTR5_D:	.long	0x0000001b
397DBTR6_D:	.long	0x00000014
398DBTR7_D:	.long	0x00000005
399DBTR8_D:	.long	0x00000015
400DBTR9_D:	.long	0x00000006
401DBTR10_D:	.long	0x00000008
402DBTR11_D:	.long	0x00000007
403DBTR12_D:	.long	0x0000000e
404DBTR13_D:	.long	0x00000056
405DBTR14_D:	.long	0x00000006
406DBTR15_D:	.long	0x00000004
407DBTR16_D:	.long	0x00150002
408DBTR17_D:	.long	0x000c0017
409DBTR18_D:	.long	0x00000200
410DBTR19_D:	.long	0x00000040
411DBRNK0_D:	.long	0x00000001
412DBPDCNT0_D:	.long	0x00000001
413DBPDCNT1_D:	.long	0x00000001
414DBPDCNT2_D:	.long	0x00000000
415DBPDCNT3_D:	.long	0x00004010
416DBPDLCK_D:	.long	0x0000a55a
417DBPDRGA_D:	.long	0x00000028
418DBPDRGD_D:	.long	0x00017100
419
420DBADJ0_D:	.long	0x00000000
421DBADJ1_D:	.long	0x00000000
422DBADJ2_D:	.long	0x18061806
423DBRFCNF0_D:	.long	0x000001ff
424DBRFCNF1_D:	.long	0x08001000
425DBRFCNF2_D:	.long	0x00000000
426DBCALCNF_D:	.long	0x0000ffff
427DBRFEN_D:	.long	0x00000001
428DBACEN_D:	.long	0x00000001
429
430/*------- DDR-ECC -------*/
431ECD_ECDEN_A:	.long	0xffc1012c
432ECD_ECDEN_D:	.long	0x00000001
433ECD_INTSR_A:	.long	0xfe900024
434ECD_INTSR_D:	.long	0xffffffff
435ECD_SPACER_A:	.long	0xfe900018
436ECD_SPACER_D:	.long	SH7757LCR_SDRAM_ECC_SETTING
437ECD_MCR_A:	.long	0xfe900010
438ECD_MCR_D:	.long	0x00000001
439
440	.align 2
441exit_ddr:
442
443#if defined(CONFIG_SH_32BIT)
444	/*------- set PMB -------*/
445	write32	PASCR_A,	PASCR_29BIT_D
446	write32	MMUCR_A,	MMUCR_D
447
448	/*****************************************************************
449	 * ent	virt		phys		v	sz	c	wt
450	 * 0	0xa0000000	0x00000000	1	128M	0	1
451	 * 1	0xa8000000	0x48000000	1	128M	0	1
452	 * 5	0x88000000	0x48000000	1	128M	1	1
453	 */
454	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
455	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
456	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
457	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
458	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
459	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
460
461	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
462	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
463	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
464	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
465	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
466	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
467	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
468	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
469	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
470	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
471	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
472	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
473	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
474
475	write32	PASCR_A,	PASCR_INIT
476	mov.l	DUMMY_ADDR, r0
477	icbi	@r0
478#endif	/* if defined(CONFIG_SH_32BIT) */
479
480exit_pmb:
481	/* CPU is running on ILRAM? */
482	mov	r14, r0
483	tst	#1, r0
484	bt	1f
485
486	mov.l	_bss_start, r15
487	mov.l	_spiboot_main, r0
488100:	bsrf	r0
489	nop
490
491	.align	2
492_spiboot_main:	.long	(spiboot_main - (100b + 4))
493_bss_start:	.long	bss_start
494
4951:
496
497	write32	CCR_A,	CCR_D
498
499	rts
500	 nop
501
502	.align 4
503
504#if defined(CONFIG_SH_32BIT)
505/*------- set PMB -------*/
506PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
507PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
508PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
509PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
510PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
511PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
512PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
513PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
514PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
515PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
516PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
517PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
518PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
519PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
520PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
521PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
522
523PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
524PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
525PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
526PMB_ADDR_NOT_USE_D:	.long	0x00000000
527
528PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
529PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
530PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
531
532/*						ppn   ub v s1 s0  c  wt */
533PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
534PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
535PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
536
537PASCR_A:		.long	0xff000070
538DUMMY_ADDR:		.long	0xa0000000
539PASCR_29BIT_D:		.long	0x00000000
540PASCR_INIT:		.long	0x80000080
541MMUCR_A:		.long	0xff000010
542MMUCR_D:		.long	0x00000004	/* clear ITLB */
543#endif	/* CONFIG_SH_32BIT */
544
545CCR_A:		.long	CCR
546CCR_D:		.long	CCR_CACHE_INIT
547