1 /* 2 * Copyright (C) 2012 Renesas Solutions Corp. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <asm/processor.h> 10 #include <asm/io.h> 11 #include <asm/mmc.h> 12 #include <spi_flash.h> 13 14 int checkboard(void) 15 { 16 puts("BOARD: SH7753 EVB\n"); 17 18 return 0; 19 } 20 21 static void init_gpio(void) 22 { 23 struct gpio_regs *gpio = GPIO_BASE; 24 struct sermux_regs *sermux = SERMUX_BASE; 25 26 /* GPIO */ 27 writew(0x0000, &gpio->pacr); /* GETHER */ 28 writew(0x0001, &gpio->pbcr); /* INTC */ 29 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ 30 writew(0x0000, &gpio->pdcr); /* SPI0 */ 31 writew(0xeaff, &gpio->pecr); /* GPIO */ 32 writew(0x0000, &gpio->pfcr); /* WDT */ 33 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ 34 writew(0x0000, &gpio->phcr); /* SPI1 */ 35 writew(0x0000, &gpio->picr); /* SDHI */ 36 writew(0x0000, &gpio->pjcr); /* SCIF4 */ 37 writew(0x0003, &gpio->pkcr); /* SerMux */ 38 writew(0x0000, &gpio->plcr); /* SerMux */ 39 writew(0x0000, &gpio->pmcr); /* RIIC */ 40 writew(0x0000, &gpio->pncr); /* USB, SGPIO */ 41 writew(0x0000, &gpio->pocr); /* SGPIO */ 42 writew(0xd555, &gpio->pqcr); /* GPIO */ 43 writew(0x0000, &gpio->prcr); /* RIIC */ 44 writew(0x0000, &gpio->pscr); /* RIIC */ 45 writew(0x0000, &gpio->ptcr); /* STATUS */ 46 writeb(0x00, &gpio->pudr); 47 writew(0x5555, &gpio->pucr); /* Debug LED */ 48 writew(0x0000, &gpio->pvcr); /* RSPI */ 49 writew(0x0000, &gpio->pwcr); /* EVC */ 50 writew(0x0000, &gpio->pxcr); /* LBSC */ 51 writew(0x0000, &gpio->pycr); /* LBSC */ 52 writew(0x0000, &gpio->pzcr); /* eMMC */ 53 writew(0xfe00, &gpio->psel0); 54 writew(0x0000, &gpio->psel1); 55 writew(0x3000, &gpio->psel2); 56 writew(0xff00, &gpio->psel3); 57 writew(0x771f, &gpio->psel4); 58 writew(0x0ffc, &gpio->psel5); 59 writew(0x00ff, &gpio->psel6); 60 writew(0xfc00, &gpio->psel7); 61 62 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ 63 } 64 65 static void init_usb_phy(void) 66 { 67 struct usb_common_regs *common0 = USB0_COMMON_BASE; 68 struct usb_common_regs *common1 = USB1_COMMON_BASE; 69 struct usb0_phy_regs *phy = USB0_PHY_BASE; 70 struct usb1_port_regs *port = USB1_PORT_BASE; 71 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; 72 73 writew(0x0100, &phy->reset); /* set reset */ 74 /* port0 = USB0, port1 = USB1 */ 75 writew(0x0002, &phy->portsel); 76 writel(0x0001, &port->port1sel); /* port1 = Host */ 77 writew(0x0111, &phy->reset); /* clear reset */ 78 79 writew(0x4000, &common0->suspmode); 80 writew(0x4000, &common1->suspmode); 81 82 #if defined(__LITTLE_ENDIAN) 83 writel(0x00000000, &align->ehcidatac); 84 writel(0x00000000, &align->ohcidatac); 85 #endif 86 } 87 88 static void init_gether_mdio(void) 89 { 90 struct gpio_regs *gpio = GPIO_BASE; 91 92 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); 93 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ 94 } 95 96 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) 97 { 98 struct ether_mac_regs *ether; 99 unsigned char mac[6]; 100 unsigned long val; 101 102 eth_parse_enetaddr(mac_string, mac); 103 104 if (!channel) 105 ether = GETHER0_MAC_BASE; 106 else 107 ether = GETHER1_MAC_BASE; 108 109 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 110 writel(val, ðer->mahr); 111 val = (mac[4] << 8) | mac[5]; 112 writel(val, ðer->malr); 113 } 114 115 /***************************************************************** 116 * This PMB must be set on this timing. The lowlevel_init is run on 117 * Area 0(phys 0x00000000), so we have to map it. 118 * 119 * The new PMB table is following: 120 * ent virt phys v sz c wt 121 * 0 0xa0000000 0x40000000 1 128M 0 1 122 * 1 0xa8000000 0x48000000 1 128M 0 1 123 * 2 0xb0000000 0x50000000 1 128M 0 1 124 * 3 0xb8000000 0x58000000 1 128M 0 1 125 * 4 0x80000000 0x40000000 1 128M 1 1 126 * 5 0x88000000 0x48000000 1 128M 1 1 127 * 6 0x90000000 0x50000000 1 128M 1 1 128 * 7 0x98000000 0x58000000 1 128M 1 1 129 */ 130 static void set_pmb_on_board_init(void) 131 { 132 struct mmu_regs *mmu = MMU_BASE; 133 134 /* clear ITLB */ 135 writel(0x00000004, &mmu->mmucr); 136 137 /* delete PMB for SPIBOOT */ 138 writel(0, PMB_ADDR_BASE(0)); 139 writel(0, PMB_DATA_BASE(0)); 140 141 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ 142 /* ppn ub v s1 s0 c wt */ 143 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); 144 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); 145 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); 146 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); 147 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); 148 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); 149 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); 150 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); 151 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); 152 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); 153 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); 154 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); 155 } 156 157 int board_init(void) 158 { 159 struct gether_control_regs *gether = GETHER_CONTROL_BASE; 160 161 init_gpio(); 162 set_pmb_on_board_init(); 163 164 /* Sets TXnDLY to B'010 */ 165 writel(0x00000202, &gether->gbecont); 166 167 init_usb_phy(); 168 init_gether_mdio(); 169 170 return 0; 171 } 172 173 int dram_init(void) 174 { 175 DECLARE_GLOBAL_DATA_PTR; 176 177 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 178 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 179 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 180 181 return 0; 182 } 183 184 int board_mmc_init(bd_t *bis) 185 { 186 struct gpio_regs *gpio = GPIO_BASE; 187 188 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); 189 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ 190 udelay(1); 191 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ 192 udelay(200); 193 194 return mmcif_mmc_init(); 195 } 196 197 static int get_sh_eth_mac_raw(unsigned char *buf, int size) 198 { 199 struct spi_flash *spi; 200 int ret; 201 202 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 203 if (spi == NULL) { 204 printf("%s: spi_flash probe failed.\n", __func__); 205 return 1; 206 } 207 208 ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf); 209 if (ret) { 210 printf("%s: spi_flash read failed.\n", __func__); 211 spi_flash_free(spi); 212 return 1; 213 } 214 spi_flash_free(spi); 215 216 return 0; 217 } 218 219 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) 220 { 221 memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)], 222 SH7753EVB_ETHERNET_MAC_SIZE); 223 mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ 224 225 return 0; 226 } 227 228 static void init_ethernet_mac(void) 229 { 230 char mac_string[64]; 231 char env_string[64]; 232 int i; 233 unsigned char *buf; 234 235 buf = malloc(256); 236 if (!buf) { 237 printf("%s: malloc failed.\n", __func__); 238 return; 239 } 240 get_sh_eth_mac_raw(buf, 256); 241 242 /* Gigabit Ethernet */ 243 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { 244 get_sh_eth_mac(i, mac_string, buf); 245 if (i == 0) 246 setenv("ethaddr", mac_string); 247 else { 248 sprintf(env_string, "eth%daddr", i); 249 setenv(env_string, mac_string); 250 } 251 set_mac_to_sh_giga_eth_register(i, mac_string); 252 } 253 254 free(buf); 255 } 256 257 int board_late_init(void) 258 { 259 init_ethernet_mac(); 260 261 return 0; 262 } 263 264 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 265 { 266 int i, ret; 267 char mac_string[256]; 268 struct spi_flash *spi; 269 unsigned char *buf; 270 271 if (argc != 3) { 272 buf = malloc(256); 273 if (!buf) { 274 printf("%s: malloc failed.\n", __func__); 275 return 1; 276 } 277 278 get_sh_eth_mac_raw(buf, 256); 279 280 /* print current MAC address */ 281 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { 282 get_sh_eth_mac(i, mac_string, buf); 283 printf("GETHERC ch%d = %s\n", i, mac_string); 284 } 285 free(buf); 286 return 0; 287 } 288 289 /* new setting */ 290 memset(mac_string, 0xff, sizeof(mac_string)); 291 sprintf(mac_string, "%s\t%s", 292 argv[1], argv[2]); 293 294 /* write MAC data to SPI rom */ 295 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 296 if (!spi) { 297 printf("%s: spi_flash probe failed.\n", __func__); 298 return 1; 299 } 300 301 ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, 302 SH7753EVB_SPI_SECTOR_SIZE); 303 if (ret) { 304 printf("%s: spi_flash erase failed.\n", __func__); 305 return 1; 306 } 307 308 ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, 309 sizeof(mac_string), mac_string); 310 if (ret) { 311 printf("%s: spi_flash write failed.\n", __func__); 312 spi_flash_free(spi); 313 return 1; 314 } 315 spi_flash_free(spi); 316 317 puts("The writing of the MAC address to SPI ROM was completed.\n"); 318 319 return 0; 320 } 321 322 U_BOOT_CMD( 323 write_mac, 3, 1, do_write_mac, 324 "write MAC address for GETHERC", 325 "[GETHERC ch0] [GETHERC ch1]\n" 326 ); 327