1/*
2 * Copyright (C) 2013  Renesas Solutions Corp.
3 *
4 * SPDX-License-Identifier:    GPL-2.0+
5 */
6
7#include <config.h>
8#include <asm/processor.h>
9#include <asm/macro.h>
10
11.macro	or32, addr, data
12	mov.l \addr, r1
13	mov.l \data, r0
14	mov.l @r1, r2
15	or    r2, r0
16	mov.l r0, @r1
17.endm
18
19.macro	wait_DBCMD
20	mov.l	DBWAIT_A, r0
21	mov.l	@r0, r1
22.endm
23
24	.global lowlevel_init
25	.section	.spiboot1.text
26	.align  2
27
28lowlevel_init:
29	mov	#0, r14
30	mova	2f, r0
31	mov.l	PC_MASK, r1
32	tst	r0, r1
33	bf	2f
34
35	bra	exit_pmb
36	nop
37
38	.align	2
39
40/* If CPU runs on SDRAM (PC=0x5???????) or not. */
41PC_MASK:	.long	0x20000000
42
432:
44	mov	#1, r14
45
46	mov.l	EXPEVT_A, r0
47	mov.l	@r0, r0
48	mov.l	EXPEVT_POWER_ON_RESET, r1
49	cmp/eq	r0, r1
50	bt	1f
51
52	/*
53	 * If EXPEVT value is manual reset or tlb multipul-hit,
54	 * initialization of DBSC3 is not necessary.
55	 */
56	bra	exit_ddr
57	nop
58
591:
60	/*------- Reset -------*/
61	write32 MRSTCR0_A, MRSTCR0_D
62	write32 MRSTCR1_A, MRSTCR1_D
63
64	/* For Core Reset */
65	mov.l	DBACEN_A, r0
66	mov.l	@r0, r0
67	cmp/eq	#0, r0
68	bt	3f
69
70	/*
71	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
72	 * initialization of DDR3-SDRAM.
73	 */
74	bra	exit_ddr
75	nop
76
773:
78	/*------- DBSC3 -------*/
79	/* oscillation stabilization time */
80	wait_timer	WAIT_OSC_TIME
81
82	/* step 3 */
83	write32 DBKIND_A, DBKIND_D
84
85	/* step 4 */
86	write32 DBCONF_A, DBCONF_D
87	write32 DBTR0_A, DBTR0_D
88	write32 DBTR1_A, DBTR1_D
89	write32 DBTR2_A, DBTR2_D
90	write32 DBTR3_A, DBTR3_D
91	write32 DBTR4_A, DBTR4_D
92	write32 DBTR5_A, DBTR5_D
93	write32 DBTR6_A, DBTR6_D
94	write32 DBTR7_A, DBTR7_D
95	write32 DBTR8_A, DBTR8_D
96	write32 DBTR9_A, DBTR9_D
97	write32 DBTR10_A, DBTR10_D
98	write32 DBTR11_A, DBTR11_D
99	write32 DBTR12_A, DBTR12_D
100	write32 DBTR13_A, DBTR13_D
101	write32 DBTR14_A, DBTR14_D
102	write32 DBTR15_A, DBTR15_D
103	write32 DBTR16_A, DBTR16_D
104	write32 DBTR17_A, DBTR17_D
105	write32 DBTR18_A, DBTR18_D
106	write32 DBTR19_A, DBTR19_D
107	write32 DBRNK0_A, DBRNK0_D
108	write32 DBADJ0_A, DBADJ0_D
109	write32 DBADJ2_A, DBADJ2_D
110
111	/* step 5 */
112	write32 DBCMD_A, DBCMD_RSTL_VAL
113	wait_timer	WAIT_30US
114
115	/* step 6 */
116	write32 DBCMD_A, DBCMD_PDEN_VAL
117
118	/* step 7 */
119	write32 DBPDCNT3_A, DBPDCNT3_D
120
121	/* step 8 */
122	write32 DBPDCNT1_A, DBPDCNT1_D
123	write32 DBPDCNT2_A, DBPDCNT2_D
124	write32 DBPDLCK_A, DBPDLCK_D
125	write32 DBPDRGA_A, DBPDRGA_D
126	write32 DBPDRGD_A, DBPDRGD_D
127
128	/* step 9 */
129	wait_timer	WAIT_30US
130
131	/* step 10 */
132	write32 DBPDCNT0_A, DBPDCNT0_D
133
134	/* step 11 */
135	wait_timer	WAIT_30US
136	wait_timer	WAIT_30US
137
138	/* step 12 */
139	write32 DBCMD_A, DBCMD_WAIT_VAL
140	wait_DBCMD
141
142	/* step 13 */
143	write32 DBCMD_A, DBCMD_RSTH_VAL
144	wait_DBCMD
145
146	/* step 14 */
147	write32 DBCMD_A, DBCMD_WAIT_VAL
148	write32 DBCMD_A, DBCMD_WAIT_VAL
149	write32 DBCMD_A, DBCMD_WAIT_VAL
150	write32 DBCMD_A, DBCMD_WAIT_VAL
151
152	/* step 15 */
153	write32 DBCMD_A, DBCMD_PDXT_VAL
154
155	/* step 16 */
156	write32 DBCMD_A, DBCMD_MRS2_VAL
157
158	/* step 17 */
159	write32 DBCMD_A, DBCMD_MRS3_VAL
160
161	/* step 18 */
162	write32 DBCMD_A, DBCMD_MRS1_VAL
163
164	/* step 19 */
165	write32 DBCMD_A, DBCMD_MRS0_VAL
166	write32 DBPDNCNF_A, DBPDNCNF_D
167
168	/* step 20 */
169	write32 DBCMD_A, DBCMD_ZQCL_VAL
170
171	write32 DBCMD_A, DBCMD_REF_VAL
172	write32 DBCMD_A, DBCMD_REF_VAL
173	wait_DBCMD
174
175	/* step 21 */
176	write32	DBCALTR_A, DBCALTR_D
177
178	/* step 22 */
179	write32 DBRFCNF0_A, DBRFCNF0_D
180	write32 DBRFCNF1_A, DBRFCNF1_D
181	write32 DBRFCNF2_A, DBRFCNF2_D
182
183	/* step 23 */
184	write32 DBCALCNF_A, DBCALCNF_D
185
186	/* step 24 */
187	write32 DBRFEN_A, DBRFEN_D
188	write32 DBCMD_A, DBCMD_SRXT_VAL
189
190	/* step 25 */
191	write32 DBACEN_A, DBACEN_D
192
193	/* step 26 */
194	wait_DBCMD
195
196	bra	exit_ddr
197	nop
198
199	.align 2
200
201EXPEVT_A:		.long	0xff000024
202EXPEVT_POWER_ON_RESET:	.long	0x00000000
203
204/*------- Reset -------*/
205MRSTCR0_A:	.long	0xffd50030
206MRSTCR0_D:	.long	0xfe1ffe7f
207MRSTCR1_A:	.long	0xffd50034
208MRSTCR1_D:	.long	0xfff3ffff
209
210/*------- DBSC3 -------*/
211DBCMD_A:	.long	0xfe800018
212DBKIND_A:	.long	0xfe800020
213DBCONF_A:	.long	0xfe800024
214DBTR0_A:	.long	0xfe800040
215DBTR1_A:	.long	0xfe800044
216DBTR2_A:	.long	0xfe800048
217DBTR3_A:	.long	0xfe800050
218DBTR4_A:	.long	0xfe800054
219DBTR5_A:	.long	0xfe800058
220DBTR6_A:	.long	0xfe80005c
221DBTR7_A:	.long	0xfe800060
222DBTR8_A:	.long	0xfe800064
223DBTR9_A:	.long	0xfe800068
224DBTR10_A:	.long	0xfe80006c
225DBTR11_A:	.long	0xfe800070
226DBTR12_A:	.long	0xfe800074
227DBTR13_A:	.long	0xfe800078
228DBTR14_A:	.long	0xfe80007c
229DBTR15_A:	.long	0xfe800080
230DBTR16_A:	.long	0xfe800084
231DBTR17_A:	.long	0xfe800088
232DBTR18_A:	.long	0xfe80008c
233DBTR19_A:	.long	0xfe800090
234DBRNK0_A:	.long	0xfe800100
235DBPDCNT0_A:	.long	0xfe800200
236DBPDCNT1_A:	.long	0xfe800204
237DBPDCNT2_A:	.long	0xfe800208
238DBPDCNT3_A:	.long	0xfe80020c
239DBPDLCK_A:	.long	0xfe800280
240DBPDRGA_A:	.long	0xfe800290
241DBPDRGD_A:	.long	0xfe8002a0
242DBADJ0_A:	.long	0xfe8000c0
243DBADJ2_A:	.long	0xfe8000c8
244DBRFCNF0_A:	.long	0xfe8000e0
245DBRFCNF1_A:	.long	0xfe8000e4
246DBRFCNF2_A:	.long	0xfe8000e8
247DBCALCNF_A:	.long	0xfe8000f4
248DBRFEN_A:	.long	0xfe800014
249DBACEN_A:	.long	0xfe800010
250DBWAIT_A:	.long	0xfe80001c
251DBCALTR_A:	.long	0xfe8000f8
252DBPDNCNF_A:	.long	0xfe800180
253
254WAIT_OSC_TIME:	.long	6000
255WAIT_30US:	.long	13333
256
257DBCMD_RSTL_VAL:	.long	0x20000000
258DBCMD_PDEN_VAL:	.long	0x1000d73c
259DBCMD_WAIT_VAL:	.long	0x0000d73c
260DBCMD_RSTH_VAL:	.long	0x2100d73c
261DBCMD_PDXT_VAL:	.long	0x110000c8
262DBCMD_MRS0_VAL:	.long	0x28000930
263DBCMD_MRS1_VAL:	.long	0x29000004
264DBCMD_MRS2_VAL:	.long	0x2a000008
265DBCMD_MRS3_VAL:	.long	0x2b000000
266DBCMD_ZQCL_VAL:	.long	0x03000200
267DBCMD_REF_VAL:	.long	0x0c000000
268DBCMD_SRXT_VAL:	.long	0x19000000
269DBKIND_D:	.long	0x00000007
270DBCONF_D:	.long	0x0f030a01
271DBTR0_D:	.long	0x00000007
272DBTR1_D:	.long	0x00000006
273DBTR2_D:	.long	0x00000000
274DBTR3_D:	.long	0x00000007
275DBTR4_D:	.long	0x00070007
276DBTR5_D:	.long	0x0000001b
277DBTR6_D:	.long	0x00000014
278DBTR7_D:	.long	0x00000004
279DBTR8_D:	.long	0x00000014
280DBTR9_D:	.long	0x00000004
281DBTR10_D:	.long	0x00000008
282DBTR11_D:	.long	0x00000007
283DBTR12_D:	.long	0x0000000e
284DBTR13_D:	.long	0x000000a0
285DBTR14_D:	.long	0x00060006
286DBTR15_D:	.long	0x00000003
287DBTR16_D:	.long	0x00160002
288DBTR17_D:	.long	0x000c0000
289DBTR18_D:	.long	0x00000200
290DBTR19_D:	.long	0x00000040
291DBRNK0_D:	.long	0x00000001
292DBPDCNT0_D:	.long	0x00000001
293DBPDCNT1_D:	.long	0x00000001
294DBPDCNT2_D:	.long	0x00000000
295DBPDCNT3_D:	.long	0x00004010
296DBPDLCK_D:	.long	0x0000a55a
297DBPDRGA_D:	.long	0x00000028
298DBPDRGD_D:	.long	0x00017100
299
300DBADJ0_D:	.long	0x00010000
301DBADJ2_D:	.long	0x18061806
302DBRFCNF0_D:	.long	0x000001ff
303DBRFCNF1_D:	.long	0x00081040
304DBRFCNF2_D:	.long	0x00000000
305DBCALCNF_D:	.long	0x0000ffff
306DBRFEN_D:	.long	0x00000001
307DBACEN_D:	.long	0x00000001
308DBCALTR_D:	.long	0x08200820
309DBPDNCNF_D:	.long	0x00000001
310
311	.align 2
312exit_ddr:
313#if defined(CONFIG_SH_32BIT)
314	/*------- set PMB -------*/
315	write32	PASCR_A,	PASCR_29BIT_D
316	write32	MMUCR_A,	MMUCR_D
317
318	/*****************************************************************
319	 * ent	virt		phys		v	sz	c	wt
320	 * 0	0xa0000000	0x00000000	1	128M	0	1
321	 * 1	0xa8000000	0x48000000	1	128M	0	1
322	 * 5	0x88000000	0x48000000	1	128M	1	1
323	 */
324	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
325	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
326	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
327	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
328	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
329	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
330
331	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
332	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
333	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
334	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
335	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
336	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
337	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
338	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
339	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
340	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
341	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
342	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
343	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
344
345	write32	PASCR_A,	PASCR_INIT
346	mov.l	DUMMY_ADDR, r0
347	icbi	@r0
348#endif	/* if defined(CONFIG_SH_32BIT) */
349
350exit_pmb:
351	/* CPU is running on ILRAM? */
352	mov	r14, r0
353	tst	#1, r0
354	bt	1f
355
356	mov.l	_stack_ilram, r15
357	mov.l	_spiboot_main, r0
358100:	bsrf	r0
359	nop
360
361	.align	2
362_spiboot_main:	.long	(spiboot_main - (100b + 4))
363_stack_ilram:	.long	0xe5204000
364
3651:
366	write32	CCR_A,	CCR_D
367
368	rts
369	 nop
370
371	.align 2
372
373#if defined(CONFIG_SH_32BIT)
374/*------- set PMB -------*/
375PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
376PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
377PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
378PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
379PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
380PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
381PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
382PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
383PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
384PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
385PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
386PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
387PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
388PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
389PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
390PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
391
392PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
393PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
394PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
395PMB_ADDR_NOT_USE_D:	.long	0x00000000
396
397PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
398PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
399PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
400
401/*						ppn   ub v s1 s0  c  wt */
402PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
403PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
404PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
405
406PASCR_A:		.long	0xff000070
407DUMMY_ADDR:		.long	0xa0000000
408PASCR_29BIT_D:		.long	0x00000000
409PASCR_INIT:		.long	0x80000080
410MMUCR_A:		.long	0xff000010
411MMUCR_D:		.long	0x00000004	/* clear ITLB */
412#endif	/* CONFIG_SH_32BIT */
413
414CCR_A:		.long	CCR
415CCR_D:		.long	CCR_CACHE_INIT
416