1 /* 2 * Copyright (C) 2012 Renesas Solutions Corp. 3 * 4 * This file is subject to the terms and conditions of the GNU Lesser 5 * General Public License. See the file "COPYING.LIB" in the main 6 * directory of this archive for more details. 7 */ 8 9 #include <common.h> 10 11 #define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE 12 #define CONFIG_SPI_ADDR 0x00000000 13 #define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN 14 #define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE 15 16 #define SPIWDMADR 0xFE001018 17 #define SPIWDMCNTR 0xFE001020 18 #define SPIDMCOR 0xFE001028 19 #define SPIDMINTSR 0xFE001188 20 #define SPIDMINTMR 0xFE001190 21 22 #define SPIDMINTSR_DMEND 0x00000004 23 24 #define TBR 0xFE002000 25 #define RBR 0xFE002000 26 27 #define CR1 0xFE002008 28 #define CR2 0xFE002010 29 #define CR3 0xFE002018 30 #define CR4 0xFE002020 31 32 /* CR1 */ 33 #define SPI_TBE 0x80 34 #define SPI_TBF 0x40 35 #define SPI_RBE 0x20 36 #define SPI_RBF 0x10 37 #define SPI_PFONRD 0x08 38 #define SPI_SSDB 0x04 39 #define SPI_SSD 0x02 40 #define SPI_SSA 0x01 41 42 /* CR2 */ 43 #define SPI_RSTF 0x80 44 #define SPI_LOOPBK 0x40 45 #define SPI_CPOL 0x20 46 #define SPI_CPHA 0x10 47 #define SPI_L1M0 0x08 48 49 /* CR4 */ 50 #define SPI_TBEI 0x80 51 #define SPI_TBFI 0x40 52 #define SPI_RBEI 0x20 53 #define SPI_RBFI 0x10 54 #define SPI_SpiS0 0x02 55 #define SPI_SSS 0x01 56 57 #define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val 58 #define spi_read(addr) (*(volatile unsigned long *)(addr)) 59 60 /* M25P80 */ 61 #define M25_READ 0x03 62 63 #define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) 64 static void __uses_spiboot2 spi_reset(void) 65 { 66 int timeout = 0x00100000; 67 68 /* Make sure the last transaction is finalized */ 69 spi_write(0x00, CR3); 70 spi_write(0x02, CR1); 71 while (!(spi_read(CR4) & SPI_SpiS0)) { 72 if (timeout-- < 0) 73 break; 74 } 75 spi_write(0x00, CR1); 76 77 spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ 78 spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); 79 80 spi_write(0, SPIDMCOR); 81 } 82 83 static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, 84 unsigned long len) 85 { 86 spi_write(M25_READ, TBR); 87 spi_write((addr >> 16) & 0xFF, TBR); 88 spi_write((addr >> 8) & 0xFF, TBR); 89 spi_write(addr & 0xFF, TBR); 90 91 spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); 92 spi_write((unsigned long)buf, SPIWDMADR); 93 spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); 94 spi_write(1, SPIDMCOR); 95 96 spi_write(0xff, CR3); 97 spi_write(spi_read(CR1) | SPI_SSDB, CR1); 98 spi_write(spi_read(CR1) | SPI_SSA, CR1); 99 100 while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) 101 ; 102 103 /* Nagate SP0-SS0 */ 104 spi_write(0, CR1); 105 } 106 107 void __uses_spiboot2 spiboot_main(void) 108 { 109 void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; 110 111 spi_reset(); 112 spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, 113 CONFIG_SPI_LENGTH); 114 115 _start(); 116 } 117