1 /*
2  * Copyright (C) 2012  Renesas Solutions Corp.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <malloc.h>
25 #include <asm/processor.h>
26 #include <asm/io.h>
27 #include <asm/mmc.h>
28 #include <spi_flash.h>
29 
30 int checkboard(void)
31 {
32 	puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
33 
34 	return 0;
35 }
36 
37 static void init_gpio(void)
38 {
39 	struct gpio_regs *gpio = GPIO_BASE;
40 	struct sermux_regs *sermux = SERMUX_BASE;
41 
42 	/* GPIO */
43 	writew(0x0000, &gpio->pacr);	/* GETHER */
44 	writew(0x0001, &gpio->pbcr);	/* INTC */
45 	writew(0x0000, &gpio->pccr);	/* PWMU, INTC */
46 	writew(0xeaff, &gpio->pecr);	/* GPIO */
47 	writew(0x0000, &gpio->pfcr);	/* WDT */
48 	writew(0x0000, &gpio->phcr);	/* SPI1 */
49 	writew(0x0000, &gpio->picr);	/* SDHI */
50 	writew(0x0003, &gpio->pkcr);	/* SerMux */
51 	writew(0x0000, &gpio->plcr);	/* SerMux */
52 	writew(0x0000, &gpio->pmcr);	/* RIIC */
53 	writew(0x0000, &gpio->pncr);	/* USB, SGPIO */
54 	writew(0x0000, &gpio->pocr);	/* SGPIO */
55 	writew(0xd555, &gpio->pqcr);	/* GPIO */
56 	writew(0x0000, &gpio->prcr);	/* RIIC */
57 	writew(0x0000, &gpio->pscr);	/* RIIC */
58 	writeb(0x00, &gpio->pudr);
59 	writew(0x5555, &gpio->pucr);	/* Debug LED */
60 	writew(0x0000, &gpio->pvcr);	/* RSPI */
61 	writew(0x0000, &gpio->pwcr);	/* EVC */
62 	writew(0x0000, &gpio->pxcr);	/* LBSC */
63 	writew(0x0000, &gpio->pycr);	/* LBSC */
64 	writew(0x0000, &gpio->pzcr);	/* eMMC */
65 	writew(0xfe00, &gpio->psel0);
66 	writew(0xff00, &gpio->psel3);
67 	writew(0x771f, &gpio->psel4);
68 	writew(0x00ff, &gpio->psel6);
69 	writew(0xfc00, &gpio->psel7);
70 
71 	writeb(0x10, &sermux->smr0);	/* SMR0: SerMux mode 0 */
72 }
73 
74 static void init_usb_phy(void)
75 {
76 	struct usb_common_regs *common0 = USB0_COMMON_BASE;
77 	struct usb_common_regs *common1 = USB1_COMMON_BASE;
78 	struct usb0_phy_regs *phy = USB0_PHY_BASE;
79 	struct usb1_port_regs *port = USB1_PORT_BASE;
80 	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
81 
82 	writew(0x0100, &phy->reset);		/* set reset */
83 	/* port0 = USB0, port1 = USB1 */
84 	writew(0x0002, &phy->portsel);
85 	writel(0x0001, &port->port1sel);	/* port1 = Host */
86 	writew(0x0111, &phy->reset);		/* clear reset */
87 
88 	writew(0x4000, &common0->suspmode);
89 	writew(0x4000, &common1->suspmode);
90 
91 #if defined(__LITTLE_ENDIAN)
92 	writel(0x00000000, &align->ehcidatac);
93 	writel(0x00000000, &align->ohcidatac);
94 #endif
95 }
96 
97 static void init_gether_mdio(void)
98 {
99 	struct gpio_regs *gpio = GPIO_BASE;
100 
101 	writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
102 	writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr);	/* Use ET0-MDIO */
103 }
104 
105 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
106 {
107 	struct ether_mac_regs *ether;
108 	unsigned char mac[6];
109 	unsigned long val;
110 
111 	eth_parse_enetaddr(mac_string, mac);
112 
113 	if (!channel)
114 		ether = GETHER0_MAC_BASE;
115 	else
116 		ether = GETHER1_MAC_BASE;
117 
118 	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
119 	writel(val, &ether->mahr);
120 	val = (mac[4] << 8) | mac[5];
121 	writel(val, &ether->malr);
122 }
123 
124 /*****************************************************************
125  * This PMB must be set on this timing. The lowlevel_init is run on
126  * Area 0(phys 0x00000000), so we have to map it.
127  *
128  * The new PMB table is following:
129  * ent	virt		phys		v	sz	c	wt
130  * 0	0xa0000000	0x40000000	1	128M	0	1
131  * 1	0xa8000000	0x48000000	1	128M	0	1
132  * 2	0xb0000000	0x50000000	1	128M	0	1
133  * 3	0xb8000000	0x58000000	1	128M	0	1
134  * 4	0x80000000	0x40000000	1	128M	1	1
135  * 5	0x88000000	0x48000000	1	128M	1	1
136  * 6	0x90000000	0x50000000	1	128M	1	1
137  * 7	0x98000000	0x58000000	1	128M	1	1
138  */
139 static void set_pmb_on_board_init(void)
140 {
141 	struct mmu_regs *mmu = MMU_BASE;
142 
143 	/* clear ITLB */
144 	writel(0x00000004, &mmu->mmucr);
145 
146 	/* delete PMB for SPIBOOT */
147 	writel(0, PMB_ADDR_BASE(0));
148 	writel(0, PMB_DATA_BASE(0));
149 
150 	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
151 	/*			ppn  ub v s1 s0  c  wt */
152 	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
153 	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
154 	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
155 	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
156 	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
157 	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
158 	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
159 	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
160 	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
161 	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
162 	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
163 	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
164 }
165 
166 int board_init(void)
167 {
168 	init_gpio();
169 	set_pmb_on_board_init();
170 
171 	init_usb_phy();
172 	init_gether_mdio();
173 
174 	return 0;
175 }
176 
177 int dram_init(void)
178 {
179 	DECLARE_GLOBAL_DATA_PTR;
180 
181 	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
182 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
183 	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
184 
185 	return 0;
186 }
187 
188 int board_mmc_init(bd_t *bis)
189 {
190 	struct gpio_regs *gpio = GPIO_BASE;
191 
192 	writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
193 	writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
194 	udelay(1);
195 	writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr);	/* Release reset */
196 	udelay(200);
197 
198 	return mmcif_mmc_init();
199 }
200 
201 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
202 {
203 	struct spi_flash *spi;
204 	int ret;
205 
206 	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
207 	if (spi == NULL) {
208 		printf("%s: spi_flash probe failed.\n", __func__);
209 		return 1;
210 	}
211 
212 	ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
213 	if (ret) {
214 		printf("%s: spi_flash read failed.\n", __func__);
215 		spi_flash_free(spi);
216 		return 1;
217 	}
218 	spi_flash_free(spi);
219 
220 	return 0;
221 }
222 
223 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
224 {
225 	memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
226 		SH7752EVB_ETHERNET_MAC_SIZE);
227 	mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */
228 
229 	return 0;
230 }
231 
232 static void init_ethernet_mac(void)
233 {
234 	char mac_string[64];
235 	char env_string[64];
236 	int i;
237 	unsigned char *buf;
238 
239 	buf = malloc(256);
240 	if (!buf) {
241 		printf("%s: malloc failed.\n", __func__);
242 		return;
243 	}
244 	get_sh_eth_mac_raw(buf, 256);
245 
246 	/* Gigabit Ethernet */
247 	for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
248 		get_sh_eth_mac(i, mac_string, buf);
249 		if (i == 0)
250 			setenv("ethaddr", mac_string);
251 		else {
252 			sprintf(env_string, "eth%daddr", i);
253 			setenv(env_string, mac_string);
254 		}
255 		set_mac_to_sh_giga_eth_register(i, mac_string);
256 	}
257 
258 	free(buf);
259 }
260 
261 int board_late_init(void)
262 {
263 	init_ethernet_mac();
264 
265 	return 0;
266 }
267 
268 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
269 {
270 	int i, ret;
271 	char mac_string[256];
272 	struct spi_flash *spi;
273 	unsigned char *buf;
274 
275 	if (argc != 3) {
276 		buf = malloc(256);
277 		if (!buf) {
278 			printf("%s: malloc failed.\n", __func__);
279 			return 1;
280 		}
281 
282 		get_sh_eth_mac_raw(buf, 256);
283 
284 		/* print current MAC address */
285 		for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
286 			get_sh_eth_mac(i, mac_string, buf);
287 			printf("GETHERC ch%d = %s\n", i, mac_string);
288 		}
289 		free(buf);
290 		return 0;
291 	}
292 
293 	/* new setting */
294 	memset(mac_string, 0xff, sizeof(mac_string));
295 	sprintf(mac_string, "%s\t%s",
296 		argv[1], argv[2]);
297 
298 	/* write MAC data to SPI rom */
299 	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
300 	if (!spi) {
301 		printf("%s: spi_flash probe failed.\n", __func__);
302 		return 1;
303 	}
304 
305 	ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
306 				SH7752EVB_SPI_SECTOR_SIZE);
307 	if (ret) {
308 		printf("%s: spi_flash erase failed.\n", __func__);
309 		return 1;
310 	}
311 
312 	ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
313 				sizeof(mac_string), mac_string);
314 	if (ret) {
315 		printf("%s: spi_flash write failed.\n", __func__);
316 		spi_flash_free(spi);
317 		return 1;
318 	}
319 	spi_flash_free(spi);
320 
321 	puts("The writing of the MAC address to SPI ROM was completed.\n");
322 
323 	return 0;
324 }
325 
326 U_BOOT_CMD(
327 	write_mac,	3,	1,	do_write_mac,
328 	"write MAC address for GETHERC",
329 	"[GETHERC ch0] [GETHERC ch1]\n"
330 );
331