1 /* 2 * Copyright (C) 2012 Renesas Solutions Corp. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <asm/processor.h> 10 #include <asm/io.h> 11 #include <asm/mmc.h> 12 #include <spi.h> 13 #include <spi_flash.h> 14 15 int checkboard(void) 16 { 17 puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); 18 19 return 0; 20 } 21 22 static void init_gpio(void) 23 { 24 struct gpio_regs *gpio = GPIO_BASE; 25 struct sermux_regs *sermux = SERMUX_BASE; 26 27 /* GPIO */ 28 writew(0x0000, &gpio->pacr); /* GETHER */ 29 writew(0x0001, &gpio->pbcr); /* INTC */ 30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ 31 writew(0xeaff, &gpio->pecr); /* GPIO */ 32 writew(0x0000, &gpio->pfcr); /* WDT */ 33 writew(0x0000, &gpio->phcr); /* SPI1 */ 34 writew(0x0000, &gpio->picr); /* SDHI */ 35 writew(0x0003, &gpio->pkcr); /* SerMux */ 36 writew(0x0000, &gpio->plcr); /* SerMux */ 37 writew(0x0000, &gpio->pmcr); /* RIIC */ 38 writew(0x0000, &gpio->pncr); /* USB, SGPIO */ 39 writew(0x0000, &gpio->pocr); /* SGPIO */ 40 writew(0xd555, &gpio->pqcr); /* GPIO */ 41 writew(0x0000, &gpio->prcr); /* RIIC */ 42 writew(0x0000, &gpio->pscr); /* RIIC */ 43 writeb(0x00, &gpio->pudr); 44 writew(0x5555, &gpio->pucr); /* Debug LED */ 45 writew(0x0000, &gpio->pvcr); /* RSPI */ 46 writew(0x0000, &gpio->pwcr); /* EVC */ 47 writew(0x0000, &gpio->pxcr); /* LBSC */ 48 writew(0x0000, &gpio->pycr); /* LBSC */ 49 writew(0x0000, &gpio->pzcr); /* eMMC */ 50 writew(0xfe00, &gpio->psel0); 51 writew(0xff00, &gpio->psel3); 52 writew(0x771f, &gpio->psel4); 53 writew(0x00ff, &gpio->psel6); 54 writew(0xfc00, &gpio->psel7); 55 56 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ 57 } 58 59 static void init_usb_phy(void) 60 { 61 struct usb_common_regs *common0 = USB0_COMMON_BASE; 62 struct usb_common_regs *common1 = USB1_COMMON_BASE; 63 struct usb0_phy_regs *phy = USB0_PHY_BASE; 64 struct usb1_port_regs *port = USB1_PORT_BASE; 65 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; 66 67 writew(0x0100, &phy->reset); /* set reset */ 68 /* port0 = USB0, port1 = USB1 */ 69 writew(0x0002, &phy->portsel); 70 writel(0x0001, &port->port1sel); /* port1 = Host */ 71 writew(0x0111, &phy->reset); /* clear reset */ 72 73 writew(0x4000, &common0->suspmode); 74 writew(0x4000, &common1->suspmode); 75 76 #if defined(__LITTLE_ENDIAN) 77 writel(0x00000000, &align->ehcidatac); 78 writel(0x00000000, &align->ohcidatac); 79 #endif 80 } 81 82 static void init_gether_mdio(void) 83 { 84 struct gpio_regs *gpio = GPIO_BASE; 85 86 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); 87 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ 88 } 89 90 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) 91 { 92 struct ether_mac_regs *ether; 93 unsigned char mac[6]; 94 unsigned long val; 95 96 eth_parse_enetaddr(mac_string, mac); 97 98 if (!channel) 99 ether = GETHER0_MAC_BASE; 100 else 101 ether = GETHER1_MAC_BASE; 102 103 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 104 writel(val, ðer->mahr); 105 val = (mac[4] << 8) | mac[5]; 106 writel(val, ðer->malr); 107 } 108 109 /***************************************************************** 110 * This PMB must be set on this timing. The lowlevel_init is run on 111 * Area 0(phys 0x00000000), so we have to map it. 112 * 113 * The new PMB table is following: 114 * ent virt phys v sz c wt 115 * 0 0xa0000000 0x40000000 1 128M 0 1 116 * 1 0xa8000000 0x48000000 1 128M 0 1 117 * 2 0xb0000000 0x50000000 1 128M 0 1 118 * 3 0xb8000000 0x58000000 1 128M 0 1 119 * 4 0x80000000 0x40000000 1 128M 1 1 120 * 5 0x88000000 0x48000000 1 128M 1 1 121 * 6 0x90000000 0x50000000 1 128M 1 1 122 * 7 0x98000000 0x58000000 1 128M 1 1 123 */ 124 static void set_pmb_on_board_init(void) 125 { 126 struct mmu_regs *mmu = MMU_BASE; 127 128 /* clear ITLB */ 129 writel(0x00000004, &mmu->mmucr); 130 131 /* delete PMB for SPIBOOT */ 132 writel(0, PMB_ADDR_BASE(0)); 133 writel(0, PMB_DATA_BASE(0)); 134 135 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ 136 /* ppn ub v s1 s0 c wt */ 137 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); 138 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); 139 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); 140 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); 141 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); 142 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); 143 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); 144 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); 145 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); 146 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); 147 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); 148 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); 149 } 150 151 int board_init(void) 152 { 153 init_gpio(); 154 set_pmb_on_board_init(); 155 156 init_usb_phy(); 157 init_gether_mdio(); 158 159 return 0; 160 } 161 162 int dram_init(void) 163 { 164 DECLARE_GLOBAL_DATA_PTR; 165 166 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 167 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 168 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 169 170 return 0; 171 } 172 173 int board_mmc_init(bd_t *bis) 174 { 175 struct gpio_regs *gpio = GPIO_BASE; 176 177 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); 178 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ 179 udelay(1); 180 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ 181 udelay(200); 182 183 return mmcif_mmc_init(); 184 } 185 186 static int get_sh_eth_mac_raw(unsigned char *buf, int size) 187 { 188 struct spi_flash *spi; 189 int ret; 190 191 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 192 if (spi == NULL) { 193 printf("%s: spi_flash probe failed.\n", __func__); 194 return 1; 195 } 196 197 ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); 198 if (ret) { 199 printf("%s: spi_flash read failed.\n", __func__); 200 spi_flash_free(spi); 201 return 1; 202 } 203 spi_flash_free(spi); 204 205 return 0; 206 } 207 208 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) 209 { 210 memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], 211 SH7752EVB_ETHERNET_MAC_SIZE); 212 mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ 213 214 return 0; 215 } 216 217 static void init_ethernet_mac(void) 218 { 219 char mac_string[64]; 220 char env_string[64]; 221 int i; 222 unsigned char *buf; 223 224 buf = malloc(256); 225 if (!buf) { 226 printf("%s: malloc failed.\n", __func__); 227 return; 228 } 229 get_sh_eth_mac_raw(buf, 256); 230 231 /* Gigabit Ethernet */ 232 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { 233 get_sh_eth_mac(i, mac_string, buf); 234 if (i == 0) 235 setenv("ethaddr", mac_string); 236 else { 237 sprintf(env_string, "eth%daddr", i); 238 setenv(env_string, mac_string); 239 } 240 set_mac_to_sh_giga_eth_register(i, mac_string); 241 } 242 243 free(buf); 244 } 245 246 int board_late_init(void) 247 { 248 init_ethernet_mac(); 249 250 return 0; 251 } 252 253 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 254 { 255 int i, ret; 256 char mac_string[256]; 257 struct spi_flash *spi; 258 unsigned char *buf; 259 260 if (argc != 3) { 261 buf = malloc(256); 262 if (!buf) { 263 printf("%s: malloc failed.\n", __func__); 264 return 1; 265 } 266 267 get_sh_eth_mac_raw(buf, 256); 268 269 /* print current MAC address */ 270 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { 271 get_sh_eth_mac(i, mac_string, buf); 272 printf("GETHERC ch%d = %s\n", i, mac_string); 273 } 274 free(buf); 275 return 0; 276 } 277 278 /* new setting */ 279 memset(mac_string, 0xff, sizeof(mac_string)); 280 sprintf(mac_string, "%s\t%s", 281 argv[1], argv[2]); 282 283 /* write MAC data to SPI rom */ 284 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 285 if (!spi) { 286 printf("%s: spi_flash probe failed.\n", __func__); 287 return 1; 288 } 289 290 ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, 291 SH7752EVB_SPI_SECTOR_SIZE); 292 if (ret) { 293 printf("%s: spi_flash erase failed.\n", __func__); 294 return 1; 295 } 296 297 ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, 298 sizeof(mac_string), mac_string); 299 if (ret) { 300 printf("%s: spi_flash write failed.\n", __func__); 301 spi_flash_free(spi); 302 return 1; 303 } 304 spi_flash_free(spi); 305 306 puts("The writing of the MAC address to SPI ROM was completed.\n"); 307 308 return 0; 309 } 310 311 U_BOOT_CMD( 312 write_mac, 3, 1, do_write_mac, 313 "write MAC address for GETHERC", 314 "[GETHERC ch0] [GETHERC ch1]\n" 315 ); 316