1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2012  Renesas Solutions Corp.
4 */
5
6#include <config.h>
7#include <asm/processor.h>
8#include <asm/macro.h>
9
10.macro	or32, addr, data
11	mov.l \addr, r1
12	mov.l \data, r0
13	mov.l @r1, r2
14	or    r2, r0
15	mov.l r0, @r1
16.endm
17
18.macro	wait_DBCMD
19	mov.l	DBWAIT_A, r0
20	mov.l	@r0, r1
21.endm
22
23	.global lowlevel_init
24	.section	.spiboot1.text
25	.align  2
26
27lowlevel_init:
28	/*------- GPIO -------*/
29	write16 PDCR_A,	PDCR_D		! SPI0
30	write16 PGCR_A,	PGCR_D		! SPI0, GETHER MDIO gate(PTG1)
31	write16 PJCR_A,	PJCR_D		! SCIF4
32	write16 PTCR_A,	PTCR_D		! STATUS
33	write16 PSEL1_A, PSEL1_D	! SPI0
34	write16 PSEL2_A, PSEL2_D	! SPI0
35	write16 PSEL5_A, PSEL5_D	! STATUS
36
37	bra	exit_gpio
38	nop
39
40	.align	2
41
42/*------- GPIO -------*/
43PDCR_A:		.long	0xffec0006
44PGCR_A:		.long	0xffec000c
45PJCR_A:		.long	0xffec0012
46PTCR_A:		.long	0xffec0026
47PSEL1_A:	.long	0xffec0072
48PSEL2_A:	.long	0xffec0074
49PSEL5_A:	.long	0xffec007a
50
51PDCR_D:		.long	0x0000
52PGCR_D:		.long	0x0004
53PJCR_D:		.long	0x0000
54PTCR_D:		.long	0x0000
55PSEL1_D:	.long	0x0000
56PSEL2_D:	.long	0x3000
57PSEL5_D:	.long	0x0ffc
58
59	.align	2
60
61exit_gpio:
62	mov	#0, r14
63	mova	2f, r0
64	mov.l	PC_MASK, r1
65	tst	r0, r1
66	bf	2f
67
68	bra	exit_pmb
69	nop
70
71	.align	2
72
73/* If CPU runs on SDRAM (PC=0x5???????) or not. */
74PC_MASK:	.long	0x20000000
75
762:
77	mov	#1, r14
78
79	mov.l	EXPEVT_A, r0
80	mov.l	@r0, r0
81	mov.l	EXPEVT_POWER_ON_RESET, r1
82	cmp/eq	r0, r1
83	bt	1f
84
85	/*
86	 * If EXPEVT value is manual reset or tlb multipul-hit,
87	 * initialization of DDR3IF is not necessary.
88	 */
89	bra	exit_ddr
90	nop
91
921:
93	/*------- Reset -------*/
94	write32 MRSTCR0_A, MRSTCR0_D
95	write32 MRSTCR1_A, MRSTCR1_D
96
97	/* For Core Reset */
98	mov.l	DBACEN_A, r0
99	mov.l	@r0, r0
100	cmp/eq	#0, r0
101	bt	3f
102
103	/*
104	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
105	 * initialization of DDR3-SDRAM.
106	 */
107	bra	exit_ddr
108	nop
109
1103:
111	/*------- DDR3IF -------*/
112	/* oscillation stabilization time */
113	wait_timer	WAIT_OSC_TIME
114
115	/* step 3 */
116	write32 DBCMD_A, DBCMD_RSTL_VAL
117	wait_timer	WAIT_30US
118
119	/* step 4 */
120	write32 DBCMD_A, DBCMD_PDEN_VAL
121
122	/* step 5 */
123	write32 DBKIND_A, DBKIND_D
124
125	/* step 6 */
126	write32 DBCONF_A, DBCONF_D
127	write32 DBTR0_A, DBTR0_D
128	write32 DBTR1_A, DBTR1_D
129	write32 DBTR2_A, DBTR2_D
130	write32 DBTR3_A, DBTR3_D
131	write32 DBTR4_A, DBTR4_D
132	write32 DBTR5_A, DBTR5_D
133	write32 DBTR6_A, DBTR6_D
134	write32 DBTR7_A, DBTR7_D
135	write32 DBTR8_A, DBTR8_D
136	write32 DBTR9_A, DBTR9_D
137	write32 DBTR10_A, DBTR10_D
138	write32 DBTR11_A, DBTR11_D
139	write32 DBTR12_A, DBTR12_D
140	write32 DBTR13_A, DBTR13_D
141	write32 DBTR14_A, DBTR14_D
142	write32 DBTR15_A, DBTR15_D
143	write32 DBTR16_A, DBTR16_D
144	write32 DBTR17_A, DBTR17_D
145	write32 DBTR18_A, DBTR18_D
146	write32 DBTR19_A, DBTR19_D
147	write32 DBRNK0_A, DBRNK0_D
148
149	/* step 7 */
150	write32 DBPDCNT3_A, DBPDCNT3_D
151
152	/* step 8 */
153	write32 DBPDCNT1_A, DBPDCNT1_D
154	write32 DBPDCNT2_A, DBPDCNT2_D
155	write32 DBPDLCK_A, DBPDLCK_D
156	write32 DBPDRGA_A, DBPDRGA_D
157	write32 DBPDRGD_A, DBPDRGD_D
158
159	/* step 9 */
160	wait_timer	WAIT_30US
161
162	/* step 10 */
163	write32 DBPDCNT0_A, DBPDCNT0_D
164
165	/* step 11 */
166	wait_timer	WAIT_30US
167	wait_timer	WAIT_30US
168
169	/* step 12 */
170	write32 DBCMD_A, DBCMD_WAIT_VAL
171	wait_DBCMD
172
173	/* step 13 */
174	write32 DBCMD_A, DBCMD_RSTH_VAL
175	wait_DBCMD
176
177	/* step 14 */
178	write32 DBCMD_A, DBCMD_WAIT_VAL
179	write32 DBCMD_A, DBCMD_WAIT_VAL
180	write32 DBCMD_A, DBCMD_WAIT_VAL
181	write32 DBCMD_A, DBCMD_WAIT_VAL
182
183	/* step 15 */
184	write32 DBCMD_A, DBCMD_PDXT_VAL
185
186	/* step 16 */
187	write32 DBCMD_A, DBCMD_MRS2_VAL
188
189	/* step 17 */
190	write32 DBCMD_A, DBCMD_MRS3_VAL
191
192	/* step 18 */
193	write32 DBCMD_A, DBCMD_MRS1_VAL
194
195	/* step 19 */
196	write32 DBCMD_A, DBCMD_MRS0_VAL
197
198	/* step 20 */
199	write32 DBCMD_A, DBCMD_ZQCL_VAL
200
201	write32 DBCMD_A, DBCMD_REF_VAL
202	write32 DBCMD_A, DBCMD_REF_VAL
203	wait_DBCMD
204
205	/* step 21 */
206	write32 DBADJ0_A, DBADJ0_D
207	write32 DBADJ1_A, DBADJ1_D
208	write32 DBADJ2_A, DBADJ2_D
209
210	/* step 22 */
211	write32 DBRFCNF0_A, DBRFCNF0_D
212	write32 DBRFCNF1_A, DBRFCNF1_D
213	write32 DBRFCNF2_A, DBRFCNF2_D
214
215	/* step 23 */
216	write32 DBCALCNF_A, DBCALCNF_D
217
218	/* step 24 */
219	write32 DBRFEN_A, DBRFEN_D
220	write32 DBCMD_A, DBCMD_SRXT_VAL
221
222	/* step 25 */
223	write32 DBACEN_A, DBACEN_D
224
225	/* step 26 */
226	wait_DBCMD
227
228	bra	exit_ddr
229	nop
230
231	.align 2
232
233EXPEVT_A:		.long	0xff000024
234EXPEVT_POWER_ON_RESET:	.long	0x00000000
235
236/*------- Reset -------*/
237MRSTCR0_A:	.long	0xffd50030
238MRSTCR0_D:	.long	0xfe1ffe7f
239MRSTCR1_A:	.long	0xffd50034
240MRSTCR1_D:	.long	0xfff3ffff
241
242/*------- DDR3IF -------*/
243DBCMD_A:	.long	0xfe800018
244DBKIND_A:	.long	0xfe800020
245DBCONF_A:	.long	0xfe800024
246DBTR0_A:	.long	0xfe800040
247DBTR1_A:	.long	0xfe800044
248DBTR2_A:	.long	0xfe800048
249DBTR3_A:	.long	0xfe800050
250DBTR4_A:	.long	0xfe800054
251DBTR5_A:	.long	0xfe800058
252DBTR6_A:	.long	0xfe80005c
253DBTR7_A:	.long	0xfe800060
254DBTR8_A:	.long	0xfe800064
255DBTR9_A:	.long	0xfe800068
256DBTR10_A:	.long	0xfe80006c
257DBTR11_A:	.long	0xfe800070
258DBTR12_A:	.long	0xfe800074
259DBTR13_A:	.long	0xfe800078
260DBTR14_A:	.long	0xfe80007c
261DBTR15_A:	.long	0xfe800080
262DBTR16_A:	.long	0xfe800084
263DBTR17_A:	.long	0xfe800088
264DBTR18_A:	.long	0xfe80008c
265DBTR19_A:	.long	0xfe800090
266DBRNK0_A:	.long	0xfe800100
267DBPDCNT0_A:	.long	0xfe800200
268DBPDCNT1_A:	.long	0xfe800204
269DBPDCNT2_A:	.long	0xfe800208
270DBPDCNT3_A:	.long	0xfe80020c
271DBPDLCK_A:	.long	0xfe800280
272DBPDRGA_A:	.long	0xfe800290
273DBPDRGD_A:	.long	0xfe8002a0
274DBADJ0_A:	.long	0xfe8000c0
275DBADJ1_A:	.long	0xfe8000c4
276DBADJ2_A:	.long	0xfe8000c8
277DBRFCNF0_A:	.long	0xfe8000e0
278DBRFCNF1_A:	.long	0xfe8000e4
279DBRFCNF2_A:	.long	0xfe8000e8
280DBCALCNF_A:	.long	0xfe8000f4
281DBRFEN_A:	.long	0xfe800014
282DBACEN_A:	.long	0xfe800010
283DBWAIT_A:	.long	0xfe80001c
284
285WAIT_OSC_TIME:	.long	6000
286WAIT_30US:	.long	13333
287
288DBCMD_RSTL_VAL:	.long	0x20000000
289DBCMD_PDEN_VAL:	.long	0x1000d73c
290DBCMD_WAIT_VAL:	.long	0x0000d73c
291DBCMD_RSTH_VAL:	.long	0x2100d73c
292DBCMD_PDXT_VAL:	.long	0x110000c8
293DBCMD_MRS0_VAL:	.long	0x28000930
294DBCMD_MRS1_VAL:	.long	0x29000004
295DBCMD_MRS2_VAL:	.long	0x2a000008
296DBCMD_MRS3_VAL:	.long	0x2b000000
297DBCMD_ZQCL_VAL:	.long	0x03000200
298DBCMD_REF_VAL:	.long	0x0c000000
299DBCMD_SRXT_VAL:	.long	0x19000000
300DBKIND_D:	.long	0x00000007
301DBCONF_D:	.long	0x0f030a01
302DBTR0_D:	.long	0x00000007
303DBTR1_D:	.long	0x00000006
304DBTR2_D:	.long	0x00000000
305DBTR3_D:	.long	0x00000007
306DBTR4_D:	.long	0x00070007
307DBTR5_D:	.long	0x0000001b
308DBTR6_D:	.long	0x00000014
309DBTR7_D:	.long	0x00000005
310DBTR8_D:	.long	0x00000015
311DBTR9_D:	.long	0x00000006
312DBTR10_D:	.long	0x00000008
313DBTR11_D:	.long	0x00000007
314DBTR12_D:	.long	0x0000000e
315DBTR13_D:	.long	0x00000056
316DBTR14_D:	.long	0x00000006
317DBTR15_D:	.long	0x00000004
318DBTR16_D:	.long	0x00150002
319DBTR17_D:	.long	0x000c0017
320DBTR18_D:	.long	0x00000200
321DBTR19_D:	.long	0x00000040
322DBRNK0_D:	.long	0x00000001
323DBPDCNT0_D:	.long	0x00000001
324DBPDCNT1_D:	.long	0x00000001
325DBPDCNT2_D:	.long	0x00000000
326DBPDCNT3_D:	.long	0x00004010
327DBPDLCK_D:	.long	0x0000a55a
328DBPDRGA_D:	.long	0x00000028
329DBPDRGD_D:	.long	0x00017100
330
331DBADJ0_D:	.long	0x00000000
332DBADJ1_D:	.long	0x00000000
333DBADJ2_D:	.long	0x18061806
334DBRFCNF0_D:	.long	0x000001ff
335DBRFCNF1_D:	.long	0x08001000
336DBRFCNF2_D:	.long	0x00000000
337DBCALCNF_D:	.long	0x0000ffff
338DBRFEN_D:	.long	0x00000001
339DBACEN_D:	.long	0x00000001
340
341	.align 2
342exit_ddr:
343#if defined(CONFIG_SH_32BIT)
344	/*------- set PMB -------*/
345	write32	PASCR_A,	PASCR_29BIT_D
346	write32	MMUCR_A,	MMUCR_D
347
348	/*****************************************************************
349	 * ent	virt		phys		v	sz	c	wt
350	 * 0	0xa0000000	0x00000000	1	128M	0	1
351	 * 1	0xa8000000	0x48000000	1	128M	0	1
352	 * 5	0x88000000	0x48000000	1	128M	1	1
353	 */
354	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
355	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
356	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
357	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
358	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
359	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
360
361	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
362	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
363	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
364	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
365	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
366	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
367	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
368	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
369	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
370	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
371	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
372	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
373	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
374
375	write32	PASCR_A,	PASCR_INIT
376	mov.l	DUMMY_ADDR, r0
377	icbi	@r0
378#endif	/* if defined(CONFIG_SH_32BIT) */
379
380exit_pmb:
381	/* CPU is running on ILRAM? */
382	mov	r14, r0
383	tst	#1, r0
384	bt	1f
385
386	mov.l	_stack_ilram, r15
387	mov.l	_spiboot_main, r0
388100:	bsrf	r0
389	nop
390
391	.align	2
392_spiboot_main:	.long	(spiboot_main - (100b + 4))
393_stack_ilram:	.long	0xe5204000
394
3951:
396	write32	CCR_A,	CCR_D
397
398	rts
399	 nop
400
401	.align 2
402
403#if defined(CONFIG_SH_32BIT)
404/*------- set PMB -------*/
405PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
406PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
407PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
408PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
409PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
410PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
411PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
412PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
413PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
414PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
415PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
416PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
417PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
418PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
419PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
420PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
421
422PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
423PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
424PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
425PMB_ADDR_NOT_USE_D:	.long	0x00000000
426
427PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
428PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
429PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
430
431/*						ppn   ub v s1 s0  c  wt */
432PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
433PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
434PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
435
436PASCR_A:		.long	0xff000070
437DUMMY_ADDR:		.long	0xa0000000
438PASCR_29BIT_D:		.long	0x00000000
439PASCR_INIT:		.long	0x80000080
440MMUCR_A:		.long	0xff000010
441MMUCR_D:		.long	0x00000004	/* clear ITLB */
442#endif	/* CONFIG_SH_32BIT */
443
444CCR_A:		.long	CCR
445CCR_D:		.long	CCR_CACHE_INIT
446