1/*
2 * Copyright (C) 2012  Renesas Solutions Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#include <config.h>
21#include <version.h>
22#include <asm/processor.h>
23#include <asm/macro.h>
24
25.macro	or32, addr, data
26	mov.l \addr, r1
27	mov.l \data, r0
28	mov.l @r1, r2
29	or    r2, r0
30	mov.l r0, @r1
31.endm
32
33.macro	wait_DBCMD
34	mov.l	DBWAIT_A, r0
35	mov.l	@r0, r1
36.endm
37
38	.global lowlevel_init
39	.section	.spiboot1.text
40	.align  2
41
42lowlevel_init:
43	/*------- GPIO -------*/
44	write16 PDCR_A,	PDCR_D		! SPI0
45	write16 PGCR_A,	PGCR_D		! SPI0, GETHER MDIO gate(PTG1)
46	write16 PJCR_A,	PJCR_D		! SCIF4
47	write16 PTCR_A,	PTCR_D		! STATUS
48	write16 PSEL1_A, PSEL1_D	! SPI0
49	write16 PSEL2_A, PSEL2_D	! SPI0
50	write16 PSEL5_A, PSEL5_D	! STATUS
51
52	bra	exit_gpio
53	nop
54
55	.align	2
56
57/*------- GPIO -------*/
58PDCR_A:		.long	0xffec0006
59PGCR_A:		.long	0xffec000c
60PJCR_A:		.long	0xffec0012
61PTCR_A:		.long	0xffec0026
62PSEL1_A:	.long	0xffec0072
63PSEL2_A:	.long	0xffec0074
64PSEL5_A:	.long	0xffec007a
65
66PDCR_D:		.long	0x0000
67PGCR_D:		.long	0x0004
68PJCR_D:		.long	0x0000
69PTCR_D:		.long	0x0000
70PSEL1_D:	.long	0x0000
71PSEL2_D:	.long	0x3000
72PSEL5_D:	.long	0x0ffc
73
74	.align	2
75
76exit_gpio:
77	mov	#0, r14
78	mova	2f, r0
79	mov.l	PC_MASK, r1
80	tst	r0, r1
81	bf	2f
82
83	bra	exit_pmb
84	nop
85
86	.align	2
87
88/* If CPU runs on SDRAM (PC=0x5???????) or not. */
89PC_MASK:	.long	0x20000000
90
912:
92	mov	#1, r14
93
94	mov.l	EXPEVT_A, r0
95	mov.l	@r0, r0
96	mov.l	EXPEVT_POWER_ON_RESET, r1
97	cmp/eq	r0, r1
98	bt	1f
99
100	/*
101	 * If EXPEVT value is manual reset or tlb multipul-hit,
102	 * initialization of DDR3IF is not necessary.
103	 */
104	bra	exit_ddr
105	nop
106
1071:
108	/*------- Reset -------*/
109	write32 MRSTCR0_A, MRSTCR0_D
110	write32 MRSTCR1_A, MRSTCR1_D
111
112	/* For Core Reset */
113	mov.l	DBACEN_A, r0
114	mov.l	@r0, r0
115	cmp/eq	#0, r0
116	bt	3f
117
118	/*
119	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
120	 * initialization of DDR3-SDRAM.
121	 */
122	bra	exit_ddr
123	nop
124
1253:
126	/*------- DDR3IF -------*/
127	/* oscillation stabilization time */
128	wait_timer	WAIT_OSC_TIME
129
130	/* step 3 */
131	write32 DBCMD_A, DBCMD_RSTL_VAL
132	wait_timer	WAIT_30US
133
134	/* step 4 */
135	write32 DBCMD_A, DBCMD_PDEN_VAL
136
137	/* step 5 */
138	write32 DBKIND_A, DBKIND_D
139
140	/* step 6 */
141	write32 DBCONF_A, DBCONF_D
142	write32 DBTR0_A, DBTR0_D
143	write32 DBTR1_A, DBTR1_D
144	write32 DBTR2_A, DBTR2_D
145	write32 DBTR3_A, DBTR3_D
146	write32 DBTR4_A, DBTR4_D
147	write32 DBTR5_A, DBTR5_D
148	write32 DBTR6_A, DBTR6_D
149	write32 DBTR7_A, DBTR7_D
150	write32 DBTR8_A, DBTR8_D
151	write32 DBTR9_A, DBTR9_D
152	write32 DBTR10_A, DBTR10_D
153	write32 DBTR11_A, DBTR11_D
154	write32 DBTR12_A, DBTR12_D
155	write32 DBTR13_A, DBTR13_D
156	write32 DBTR14_A, DBTR14_D
157	write32 DBTR15_A, DBTR15_D
158	write32 DBTR16_A, DBTR16_D
159	write32 DBTR17_A, DBTR17_D
160	write32 DBTR18_A, DBTR18_D
161	write32 DBTR19_A, DBTR19_D
162	write32 DBRNK0_A, DBRNK0_D
163
164	/* step 7 */
165	write32 DBPDCNT3_A, DBPDCNT3_D
166
167	/* step 8 */
168	write32 DBPDCNT1_A, DBPDCNT1_D
169	write32 DBPDCNT2_A, DBPDCNT2_D
170	write32 DBPDLCK_A, DBPDLCK_D
171	write32 DBPDRGA_A, DBPDRGA_D
172	write32 DBPDRGD_A, DBPDRGD_D
173
174	/* step 9 */
175	wait_timer	WAIT_30US
176
177	/* step 10 */
178	write32 DBPDCNT0_A, DBPDCNT0_D
179
180	/* step 11 */
181	wait_timer	WAIT_30US
182	wait_timer	WAIT_30US
183
184	/* step 12 */
185	write32 DBCMD_A, DBCMD_WAIT_VAL
186	wait_DBCMD
187
188	/* step 13 */
189	write32 DBCMD_A, DBCMD_RSTH_VAL
190	wait_DBCMD
191
192	/* step 14 */
193	write32 DBCMD_A, DBCMD_WAIT_VAL
194	write32 DBCMD_A, DBCMD_WAIT_VAL
195	write32 DBCMD_A, DBCMD_WAIT_VAL
196	write32 DBCMD_A, DBCMD_WAIT_VAL
197
198	/* step 15 */
199	write32 DBCMD_A, DBCMD_PDXT_VAL
200
201	/* step 16 */
202	write32 DBCMD_A, DBCMD_MRS2_VAL
203
204	/* step 17 */
205	write32 DBCMD_A, DBCMD_MRS3_VAL
206
207	/* step 18 */
208	write32 DBCMD_A, DBCMD_MRS1_VAL
209
210	/* step 19 */
211	write32 DBCMD_A, DBCMD_MRS0_VAL
212
213	/* step 20 */
214	write32 DBCMD_A, DBCMD_ZQCL_VAL
215
216	write32 DBCMD_A, DBCMD_REF_VAL
217	write32 DBCMD_A, DBCMD_REF_VAL
218	wait_DBCMD
219
220	/* step 21 */
221	write32 DBADJ0_A, DBADJ0_D
222	write32 DBADJ1_A, DBADJ1_D
223	write32 DBADJ2_A, DBADJ2_D
224
225	/* step 22 */
226	write32 DBRFCNF0_A, DBRFCNF0_D
227	write32 DBRFCNF1_A, DBRFCNF1_D
228	write32 DBRFCNF2_A, DBRFCNF2_D
229
230	/* step 23 */
231	write32 DBCALCNF_A, DBCALCNF_D
232
233	/* step 24 */
234	write32 DBRFEN_A, DBRFEN_D
235	write32 DBCMD_A, DBCMD_SRXT_VAL
236
237	/* step 25 */
238	write32 DBACEN_A, DBACEN_D
239
240	/* step 26 */
241	wait_DBCMD
242
243	bra	exit_ddr
244	nop
245
246	.align 2
247
248EXPEVT_A:		.long	0xff000024
249EXPEVT_POWER_ON_RESET:	.long	0x00000000
250
251/*------- Reset -------*/
252MRSTCR0_A:	.long	0xffd50030
253MRSTCR0_D:	.long	0xfe1ffe7f
254MRSTCR1_A:	.long	0xffd50034
255MRSTCR1_D:	.long	0xfff3ffff
256
257/*------- DDR3IF -------*/
258DBCMD_A:	.long	0xfe800018
259DBKIND_A:	.long	0xfe800020
260DBCONF_A:	.long	0xfe800024
261DBTR0_A:	.long	0xfe800040
262DBTR1_A:	.long	0xfe800044
263DBTR2_A:	.long	0xfe800048
264DBTR3_A:	.long	0xfe800050
265DBTR4_A:	.long	0xfe800054
266DBTR5_A:	.long	0xfe800058
267DBTR6_A:	.long	0xfe80005c
268DBTR7_A:	.long	0xfe800060
269DBTR8_A:	.long	0xfe800064
270DBTR9_A:	.long	0xfe800068
271DBTR10_A:	.long	0xfe80006c
272DBTR11_A:	.long	0xfe800070
273DBTR12_A:	.long	0xfe800074
274DBTR13_A:	.long	0xfe800078
275DBTR14_A:	.long	0xfe80007c
276DBTR15_A:	.long	0xfe800080
277DBTR16_A:	.long	0xfe800084
278DBTR17_A:	.long	0xfe800088
279DBTR18_A:	.long	0xfe80008c
280DBTR19_A:	.long	0xfe800090
281DBRNK0_A:	.long	0xfe800100
282DBPDCNT0_A:	.long	0xfe800200
283DBPDCNT1_A:	.long	0xfe800204
284DBPDCNT2_A:	.long	0xfe800208
285DBPDCNT3_A:	.long	0xfe80020c
286DBPDLCK_A:	.long	0xfe800280
287DBPDRGA_A:	.long	0xfe800290
288DBPDRGD_A:	.long	0xfe8002a0
289DBADJ0_A:	.long	0xfe8000c0
290DBADJ1_A:	.long	0xfe8000c4
291DBADJ2_A:	.long	0xfe8000c8
292DBRFCNF0_A:	.long	0xfe8000e0
293DBRFCNF1_A:	.long	0xfe8000e4
294DBRFCNF2_A:	.long	0xfe8000e8
295DBCALCNF_A:	.long	0xfe8000f4
296DBRFEN_A:	.long	0xfe800014
297DBACEN_A:	.long	0xfe800010
298DBWAIT_A:	.long	0xfe80001c
299
300WAIT_OSC_TIME:	.long	6000
301WAIT_30US:	.long	13333
302
303DBCMD_RSTL_VAL:	.long	0x20000000
304DBCMD_PDEN_VAL:	.long	0x1000d73c
305DBCMD_WAIT_VAL:	.long	0x0000d73c
306DBCMD_RSTH_VAL:	.long	0x2100d73c
307DBCMD_PDXT_VAL:	.long	0x110000c8
308DBCMD_MRS0_VAL:	.long	0x28000930
309DBCMD_MRS1_VAL:	.long	0x29000004
310DBCMD_MRS2_VAL:	.long	0x2a000008
311DBCMD_MRS3_VAL:	.long	0x2b000000
312DBCMD_ZQCL_VAL:	.long	0x03000200
313DBCMD_REF_VAL:	.long	0x0c000000
314DBCMD_SRXT_VAL:	.long	0x19000000
315DBKIND_D:	.long	0x00000007
316DBCONF_D:	.long	0x0f030a01
317DBTR0_D:	.long	0x00000007
318DBTR1_D:	.long	0x00000006
319DBTR2_D:	.long	0x00000000
320DBTR3_D:	.long	0x00000007
321DBTR4_D:	.long	0x00070007
322DBTR5_D:	.long	0x0000001b
323DBTR6_D:	.long	0x00000014
324DBTR7_D:	.long	0x00000005
325DBTR8_D:	.long	0x00000015
326DBTR9_D:	.long	0x00000006
327DBTR10_D:	.long	0x00000008
328DBTR11_D:	.long	0x00000007
329DBTR12_D:	.long	0x0000000e
330DBTR13_D:	.long	0x00000056
331DBTR14_D:	.long	0x00000006
332DBTR15_D:	.long	0x00000004
333DBTR16_D:	.long	0x00150002
334DBTR17_D:	.long	0x000c0017
335DBTR18_D:	.long	0x00000200
336DBTR19_D:	.long	0x00000040
337DBRNK0_D:	.long	0x00000001
338DBPDCNT0_D:	.long	0x00000001
339DBPDCNT1_D:	.long	0x00000001
340DBPDCNT2_D:	.long	0x00000000
341DBPDCNT3_D:	.long	0x00004010
342DBPDLCK_D:	.long	0x0000a55a
343DBPDRGA_D:	.long	0x00000028
344DBPDRGD_D:	.long	0x00017100
345
346DBADJ0_D:	.long	0x00000000
347DBADJ1_D:	.long	0x00000000
348DBADJ2_D:	.long	0x18061806
349DBRFCNF0_D:	.long	0x000001ff
350DBRFCNF1_D:	.long	0x08001000
351DBRFCNF2_D:	.long	0x00000000
352DBCALCNF_D:	.long	0x0000ffff
353DBRFEN_D:	.long	0x00000001
354DBACEN_D:	.long	0x00000001
355
356	.align 2
357exit_ddr:
358#if defined(CONFIG_SH_32BIT)
359	/*------- set PMB -------*/
360	write32	PASCR_A,	PASCR_29BIT_D
361	write32	MMUCR_A,	MMUCR_D
362
363	/*****************************************************************
364	 * ent	virt		phys		v	sz	c	wt
365	 * 0	0xa0000000	0x00000000	1	128M	0	1
366	 * 1	0xa8000000	0x48000000	1	128M	0	1
367	 * 5	0x88000000	0x48000000	1	128M	1	1
368	 */
369	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
370	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
371	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
372	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
373	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
374	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
375
376	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
377	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
378	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
379	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
380	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
381	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
382	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
383	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
384	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
385	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
386	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
387	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
388	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
389
390	write32	PASCR_A,	PASCR_INIT
391	mov.l	DUMMY_ADDR, r0
392	icbi	@r0
393#endif	/* if defined(CONFIG_SH_32BIT) */
394
395exit_pmb:
396	/* CPU is running on ILRAM? */
397	mov	r14, r0
398	tst	#1, r0
399	bt	1f
400
401	mov.l	_stack_ilram, r15
402	mov.l	_spiboot_main, r0
403100:	bsrf	r0
404	nop
405
406	.align	2
407_spiboot_main:	.long	(spiboot_main - (100b + 4))
408_stack_ilram:	.long	0xe5204000
409
4101:
411	write32	CCR_A,	CCR_D
412
413	rts
414	 nop
415
416	.align 2
417
418#if defined(CONFIG_SH_32BIT)
419/*------- set PMB -------*/
420PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
421PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
422PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
423PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
424PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
425PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
426PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
427PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
428PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
429PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
430PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
431PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
432PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
433PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
434PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
435PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
436
437PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
438PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
439PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
440PMB_ADDR_NOT_USE_D:	.long	0x00000000
441
442PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
443PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
444PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
445
446/*						ppn   ub v s1 s0  c  wt */
447PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
448PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
449PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
450
451PASCR_A:		.long	0xff000070
452DUMMY_ADDR:		.long	0xa0000000
453PASCR_29BIT_D:		.long	0x00000000
454PASCR_INIT:		.long	0x80000080
455MMUCR_A:		.long	0xff000010
456MMUCR_D:		.long	0x00000004	/* clear ITLB */
457#endif	/* CONFIG_SH_32BIT */
458
459CCR_A:		.long	CCR
460CCR_D:		.long	CCR_CACHE_INIT
461