1/*
2 * Copyright (C) 2012  Renesas Solutions Corp.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include <config.h>
8#include <asm/processor.h>
9#include <asm/macro.h>
10
11.macro	or32, addr, data
12	mov.l \addr, r1
13	mov.l \data, r0
14	mov.l @r1, r2
15	or    r2, r0
16	mov.l r0, @r1
17.endm
18
19.macro	wait_DBCMD
20	mov.l	DBWAIT_A, r0
21	mov.l	@r0, r1
22.endm
23
24	.global lowlevel_init
25	.section	.spiboot1.text
26	.align  2
27
28lowlevel_init:
29	/*------- GPIO -------*/
30	write16 PDCR_A,	PDCR_D		! SPI0
31	write16 PGCR_A,	PGCR_D		! SPI0, GETHER MDIO gate(PTG1)
32	write16 PJCR_A,	PJCR_D		! SCIF4
33	write16 PTCR_A,	PTCR_D		! STATUS
34	write16 PSEL1_A, PSEL1_D	! SPI0
35	write16 PSEL2_A, PSEL2_D	! SPI0
36	write16 PSEL5_A, PSEL5_D	! STATUS
37
38	bra	exit_gpio
39	nop
40
41	.align	2
42
43/*------- GPIO -------*/
44PDCR_A:		.long	0xffec0006
45PGCR_A:		.long	0xffec000c
46PJCR_A:		.long	0xffec0012
47PTCR_A:		.long	0xffec0026
48PSEL1_A:	.long	0xffec0072
49PSEL2_A:	.long	0xffec0074
50PSEL5_A:	.long	0xffec007a
51
52PDCR_D:		.long	0x0000
53PGCR_D:		.long	0x0004
54PJCR_D:		.long	0x0000
55PTCR_D:		.long	0x0000
56PSEL1_D:	.long	0x0000
57PSEL2_D:	.long	0x3000
58PSEL5_D:	.long	0x0ffc
59
60	.align	2
61
62exit_gpio:
63	mov	#0, r14
64	mova	2f, r0
65	mov.l	PC_MASK, r1
66	tst	r0, r1
67	bf	2f
68
69	bra	exit_pmb
70	nop
71
72	.align	2
73
74/* If CPU runs on SDRAM (PC=0x5???????) or not. */
75PC_MASK:	.long	0x20000000
76
772:
78	mov	#1, r14
79
80	mov.l	EXPEVT_A, r0
81	mov.l	@r0, r0
82	mov.l	EXPEVT_POWER_ON_RESET, r1
83	cmp/eq	r0, r1
84	bt	1f
85
86	/*
87	 * If EXPEVT value is manual reset or tlb multipul-hit,
88	 * initialization of DDR3IF is not necessary.
89	 */
90	bra	exit_ddr
91	nop
92
931:
94	/*------- Reset -------*/
95	write32 MRSTCR0_A, MRSTCR0_D
96	write32 MRSTCR1_A, MRSTCR1_D
97
98	/* For Core Reset */
99	mov.l	DBACEN_A, r0
100	mov.l	@r0, r0
101	cmp/eq	#0, r0
102	bt	3f
103
104	/*
105	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
106	 * initialization of DDR3-SDRAM.
107	 */
108	bra	exit_ddr
109	nop
110
1113:
112	/*------- DDR3IF -------*/
113	/* oscillation stabilization time */
114	wait_timer	WAIT_OSC_TIME
115
116	/* step 3 */
117	write32 DBCMD_A, DBCMD_RSTL_VAL
118	wait_timer	WAIT_30US
119
120	/* step 4 */
121	write32 DBCMD_A, DBCMD_PDEN_VAL
122
123	/* step 5 */
124	write32 DBKIND_A, DBKIND_D
125
126	/* step 6 */
127	write32 DBCONF_A, DBCONF_D
128	write32 DBTR0_A, DBTR0_D
129	write32 DBTR1_A, DBTR1_D
130	write32 DBTR2_A, DBTR2_D
131	write32 DBTR3_A, DBTR3_D
132	write32 DBTR4_A, DBTR4_D
133	write32 DBTR5_A, DBTR5_D
134	write32 DBTR6_A, DBTR6_D
135	write32 DBTR7_A, DBTR7_D
136	write32 DBTR8_A, DBTR8_D
137	write32 DBTR9_A, DBTR9_D
138	write32 DBTR10_A, DBTR10_D
139	write32 DBTR11_A, DBTR11_D
140	write32 DBTR12_A, DBTR12_D
141	write32 DBTR13_A, DBTR13_D
142	write32 DBTR14_A, DBTR14_D
143	write32 DBTR15_A, DBTR15_D
144	write32 DBTR16_A, DBTR16_D
145	write32 DBTR17_A, DBTR17_D
146	write32 DBTR18_A, DBTR18_D
147	write32 DBTR19_A, DBTR19_D
148	write32 DBRNK0_A, DBRNK0_D
149
150	/* step 7 */
151	write32 DBPDCNT3_A, DBPDCNT3_D
152
153	/* step 8 */
154	write32 DBPDCNT1_A, DBPDCNT1_D
155	write32 DBPDCNT2_A, DBPDCNT2_D
156	write32 DBPDLCK_A, DBPDLCK_D
157	write32 DBPDRGA_A, DBPDRGA_D
158	write32 DBPDRGD_A, DBPDRGD_D
159
160	/* step 9 */
161	wait_timer	WAIT_30US
162
163	/* step 10 */
164	write32 DBPDCNT0_A, DBPDCNT0_D
165
166	/* step 11 */
167	wait_timer	WAIT_30US
168	wait_timer	WAIT_30US
169
170	/* step 12 */
171	write32 DBCMD_A, DBCMD_WAIT_VAL
172	wait_DBCMD
173
174	/* step 13 */
175	write32 DBCMD_A, DBCMD_RSTH_VAL
176	wait_DBCMD
177
178	/* step 14 */
179	write32 DBCMD_A, DBCMD_WAIT_VAL
180	write32 DBCMD_A, DBCMD_WAIT_VAL
181	write32 DBCMD_A, DBCMD_WAIT_VAL
182	write32 DBCMD_A, DBCMD_WAIT_VAL
183
184	/* step 15 */
185	write32 DBCMD_A, DBCMD_PDXT_VAL
186
187	/* step 16 */
188	write32 DBCMD_A, DBCMD_MRS2_VAL
189
190	/* step 17 */
191	write32 DBCMD_A, DBCMD_MRS3_VAL
192
193	/* step 18 */
194	write32 DBCMD_A, DBCMD_MRS1_VAL
195
196	/* step 19 */
197	write32 DBCMD_A, DBCMD_MRS0_VAL
198
199	/* step 20 */
200	write32 DBCMD_A, DBCMD_ZQCL_VAL
201
202	write32 DBCMD_A, DBCMD_REF_VAL
203	write32 DBCMD_A, DBCMD_REF_VAL
204	wait_DBCMD
205
206	/* step 21 */
207	write32 DBADJ0_A, DBADJ0_D
208	write32 DBADJ1_A, DBADJ1_D
209	write32 DBADJ2_A, DBADJ2_D
210
211	/* step 22 */
212	write32 DBRFCNF0_A, DBRFCNF0_D
213	write32 DBRFCNF1_A, DBRFCNF1_D
214	write32 DBRFCNF2_A, DBRFCNF2_D
215
216	/* step 23 */
217	write32 DBCALCNF_A, DBCALCNF_D
218
219	/* step 24 */
220	write32 DBRFEN_A, DBRFEN_D
221	write32 DBCMD_A, DBCMD_SRXT_VAL
222
223	/* step 25 */
224	write32 DBACEN_A, DBACEN_D
225
226	/* step 26 */
227	wait_DBCMD
228
229	bra	exit_ddr
230	nop
231
232	.align 2
233
234EXPEVT_A:		.long	0xff000024
235EXPEVT_POWER_ON_RESET:	.long	0x00000000
236
237/*------- Reset -------*/
238MRSTCR0_A:	.long	0xffd50030
239MRSTCR0_D:	.long	0xfe1ffe7f
240MRSTCR1_A:	.long	0xffd50034
241MRSTCR1_D:	.long	0xfff3ffff
242
243/*------- DDR3IF -------*/
244DBCMD_A:	.long	0xfe800018
245DBKIND_A:	.long	0xfe800020
246DBCONF_A:	.long	0xfe800024
247DBTR0_A:	.long	0xfe800040
248DBTR1_A:	.long	0xfe800044
249DBTR2_A:	.long	0xfe800048
250DBTR3_A:	.long	0xfe800050
251DBTR4_A:	.long	0xfe800054
252DBTR5_A:	.long	0xfe800058
253DBTR6_A:	.long	0xfe80005c
254DBTR7_A:	.long	0xfe800060
255DBTR8_A:	.long	0xfe800064
256DBTR9_A:	.long	0xfe800068
257DBTR10_A:	.long	0xfe80006c
258DBTR11_A:	.long	0xfe800070
259DBTR12_A:	.long	0xfe800074
260DBTR13_A:	.long	0xfe800078
261DBTR14_A:	.long	0xfe80007c
262DBTR15_A:	.long	0xfe800080
263DBTR16_A:	.long	0xfe800084
264DBTR17_A:	.long	0xfe800088
265DBTR18_A:	.long	0xfe80008c
266DBTR19_A:	.long	0xfe800090
267DBRNK0_A:	.long	0xfe800100
268DBPDCNT0_A:	.long	0xfe800200
269DBPDCNT1_A:	.long	0xfe800204
270DBPDCNT2_A:	.long	0xfe800208
271DBPDCNT3_A:	.long	0xfe80020c
272DBPDLCK_A:	.long	0xfe800280
273DBPDRGA_A:	.long	0xfe800290
274DBPDRGD_A:	.long	0xfe8002a0
275DBADJ0_A:	.long	0xfe8000c0
276DBADJ1_A:	.long	0xfe8000c4
277DBADJ2_A:	.long	0xfe8000c8
278DBRFCNF0_A:	.long	0xfe8000e0
279DBRFCNF1_A:	.long	0xfe8000e4
280DBRFCNF2_A:	.long	0xfe8000e8
281DBCALCNF_A:	.long	0xfe8000f4
282DBRFEN_A:	.long	0xfe800014
283DBACEN_A:	.long	0xfe800010
284DBWAIT_A:	.long	0xfe80001c
285
286WAIT_OSC_TIME:	.long	6000
287WAIT_30US:	.long	13333
288
289DBCMD_RSTL_VAL:	.long	0x20000000
290DBCMD_PDEN_VAL:	.long	0x1000d73c
291DBCMD_WAIT_VAL:	.long	0x0000d73c
292DBCMD_RSTH_VAL:	.long	0x2100d73c
293DBCMD_PDXT_VAL:	.long	0x110000c8
294DBCMD_MRS0_VAL:	.long	0x28000930
295DBCMD_MRS1_VAL:	.long	0x29000004
296DBCMD_MRS2_VAL:	.long	0x2a000008
297DBCMD_MRS3_VAL:	.long	0x2b000000
298DBCMD_ZQCL_VAL:	.long	0x03000200
299DBCMD_REF_VAL:	.long	0x0c000000
300DBCMD_SRXT_VAL:	.long	0x19000000
301DBKIND_D:	.long	0x00000007
302DBCONF_D:	.long	0x0f030a01
303DBTR0_D:	.long	0x00000007
304DBTR1_D:	.long	0x00000006
305DBTR2_D:	.long	0x00000000
306DBTR3_D:	.long	0x00000007
307DBTR4_D:	.long	0x00070007
308DBTR5_D:	.long	0x0000001b
309DBTR6_D:	.long	0x00000014
310DBTR7_D:	.long	0x00000005
311DBTR8_D:	.long	0x00000015
312DBTR9_D:	.long	0x00000006
313DBTR10_D:	.long	0x00000008
314DBTR11_D:	.long	0x00000007
315DBTR12_D:	.long	0x0000000e
316DBTR13_D:	.long	0x00000056
317DBTR14_D:	.long	0x00000006
318DBTR15_D:	.long	0x00000004
319DBTR16_D:	.long	0x00150002
320DBTR17_D:	.long	0x000c0017
321DBTR18_D:	.long	0x00000200
322DBTR19_D:	.long	0x00000040
323DBRNK0_D:	.long	0x00000001
324DBPDCNT0_D:	.long	0x00000001
325DBPDCNT1_D:	.long	0x00000001
326DBPDCNT2_D:	.long	0x00000000
327DBPDCNT3_D:	.long	0x00004010
328DBPDLCK_D:	.long	0x0000a55a
329DBPDRGA_D:	.long	0x00000028
330DBPDRGD_D:	.long	0x00017100
331
332DBADJ0_D:	.long	0x00000000
333DBADJ1_D:	.long	0x00000000
334DBADJ2_D:	.long	0x18061806
335DBRFCNF0_D:	.long	0x000001ff
336DBRFCNF1_D:	.long	0x08001000
337DBRFCNF2_D:	.long	0x00000000
338DBCALCNF_D:	.long	0x0000ffff
339DBRFEN_D:	.long	0x00000001
340DBACEN_D:	.long	0x00000001
341
342	.align 2
343exit_ddr:
344#if defined(CONFIG_SH_32BIT)
345	/*------- set PMB -------*/
346	write32	PASCR_A,	PASCR_29BIT_D
347	write32	MMUCR_A,	MMUCR_D
348
349	/*****************************************************************
350	 * ent	virt		phys		v	sz	c	wt
351	 * 0	0xa0000000	0x00000000	1	128M	0	1
352	 * 1	0xa8000000	0x48000000	1	128M	0	1
353	 * 5	0x88000000	0x48000000	1	128M	1	1
354	 */
355	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
356	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
357	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
358	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
359	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
360	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
361
362	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
363	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
364	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
365	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
366	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
367	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
368	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
369	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
370	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
371	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
372	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
373	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
374	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
375
376	write32	PASCR_A,	PASCR_INIT
377	mov.l	DUMMY_ADDR, r0
378	icbi	@r0
379#endif	/* if defined(CONFIG_SH_32BIT) */
380
381exit_pmb:
382	/* CPU is running on ILRAM? */
383	mov	r14, r0
384	tst	#1, r0
385	bt	1f
386
387	mov.l	_stack_ilram, r15
388	mov.l	_spiboot_main, r0
389100:	bsrf	r0
390	nop
391
392	.align	2
393_spiboot_main:	.long	(spiboot_main - (100b + 4))
394_stack_ilram:	.long	0xe5204000
395
3961:
397	write32	CCR_A,	CCR_D
398
399	rts
400	 nop
401
402	.align 2
403
404#if defined(CONFIG_SH_32BIT)
405/*------- set PMB -------*/
406PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
407PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
408PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
409PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
410PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
411PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
412PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
413PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
414PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
415PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
416PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
417PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
418PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
419PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
420PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
421PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
422
423PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
424PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
425PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
426PMB_ADDR_NOT_USE_D:	.long	0x00000000
427
428PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
429PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
430PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
431
432/*						ppn   ub v s1 s0  c  wt */
433PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
434PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
435PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
436
437PASCR_A:		.long	0xff000070
438DUMMY_ADDR:		.long	0xa0000000
439PASCR_29BIT_D:		.long	0x00000000
440PASCR_INIT:		.long	0x80000080
441MMUCR_A:		.long	0xff000010
442MMUCR_D:		.long	0x00000004	/* clear ITLB */
443#endif	/* CONFIG_SH_32BIT */
444
445CCR_A:		.long	CCR
446CCR_D:		.long	CCR_CACHE_INIT
447