1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board/renesas/salvator-x/salvator-x.c
4  *     This file is Salvator-X/Salvator-XS board support.
5  *
6  * Copyright (C) 2015-2017 Renesas Electronics Corporation
7  * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
8  */
9 
10 #include <common.h>
11 #include <malloc.h>
12 #include <netdev.h>
13 #include <dm.h>
14 #include <dm/platform_data/serial_sh.h>
15 #include <asm/processor.h>
16 #include <asm/mach-types.h>
17 #include <asm/io.h>
18 #include <linux/errno.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/gpio.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/rmobile.h>
23 #include <asm/arch/rcar-mstp.h>
24 #include <asm/arch/sh_sdhi.h>
25 #include <i2c.h>
26 #include <mmc.h>
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 #define CPGWPCR	0xE6150904
31 #define CPGWPR  0xE615090C
32 
33 #define CLK2MHZ(clk)	(clk / 1000 / 1000)
34 void s_init(void)
35 {
36 	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
37 	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
38 
39 	/* Watchdog init */
40 	writel(0xA5A5A500, &rwdt->rwtcsra);
41 	writel(0xA5A5A500, &swdt->swtcsra);
42 
43 	writel(0xA5A50000, CPGWPCR);
44 	writel(0xFFFFFFFF, CPGWPR);
45 }
46 
47 #define GSX_MSTP112		BIT(12)	/* 3DG */
48 #define TMU0_MSTP125		BIT(25)	/* secure */
49 #define TMU1_MSTP124		BIT(24)	/* non-secure */
50 #define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
51 #define DVFS_MSTP926		BIT(26)
52 #define HSUSB_MSTP704		BIT(4)	/* HSUSB */
53 
54 int board_early_init_f(void)
55 {
56 	/* TMU0,1 */		/* which use ? */
57 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
58 
59 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
60 	/* DVFS for reset */
61 	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
62 #endif
63 	return 0;
64 }
65 
66 /* SYSC */
67 /* R/- 32 Power status register 2(3DG) */
68 #define	SYSC_PWRSR2	0xE6180100
69 /* -/W 32 Power resume control register 2 (3DG) */
70 #define	SYSC_PWRONCR2	0xE618010C
71 
72 /* HSUSB block registers */
73 #define HSUSB_REG_LPSTS			0xE6590102
74 #define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
75 #define HSUSB_REG_UGCTRL2		0xE6590184
76 #define HSUSB_REG_UGCTRL2_USB0SEL	0x30
77 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
78 
79 int board_init(void)
80 {
81 	u32 cpu_type = rmobile_get_cpu_type();
82 
83 	/* adress of boot parameters */
84 	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
85 
86 	if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
87 		/* GSX: force power and clock supply */
88 		writel(0x0000001F, SYSC_PWRONCR2);
89 		while (readl(SYSC_PWRSR2) != 0x000003E0)
90 			mdelay(20);
91 
92 		mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
93 	}
94 
95 	/* USB1 pull-up */
96 	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
97 
98 	/* Configure the HSUSB block */
99 	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
100 	/* Choice USB0SEL */
101 	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
102 			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
103 	/* low power status */
104 	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
105 
106 	return 0;
107 }
108 
109 int dram_init(void)
110 {
111 	if (fdtdec_setup_mem_size_base() != 0)
112 		return -EINVAL;
113 
114 	return 0;
115 }
116 
117 int dram_init_banksize(void)
118 {
119 	fdtdec_setup_memory_banksize();
120 
121 	return 0;
122 }
123 
124 #define RST_BASE	0xE6160000
125 #define RST_CA57RESCNT	(RST_BASE + 0x40)
126 #define RST_CA53RESCNT	(RST_BASE + 0x44)
127 #define RST_RSTOUTCR	(RST_BASE + 0x58)
128 #define RST_CODE	0xA5A5000F
129 
130 void reset_cpu(ulong addr)
131 {
132 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
133 	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
134 #else
135 	/* only CA57 ? */
136 	writel(RST_CODE, RST_CA57RESCNT);
137 #endif
138 }
139