1e525d34bSNobuhiro Iwamatsu /* 2e525d34bSNobuhiro Iwamatsu * board/renesas/salvator-x/salvator-x.c 3e525d34bSNobuhiro Iwamatsu * This file is Salvator-X board support. 4e525d34bSNobuhiro Iwamatsu * 550fb0c45SMarek Vasut * Copyright (C) 2015-2017 Renesas Electronics Corporation 6e525d34bSNobuhiro Iwamatsu * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 7e525d34bSNobuhiro Iwamatsu * 8e525d34bSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0+ 9e525d34bSNobuhiro Iwamatsu */ 10e525d34bSNobuhiro Iwamatsu 11e525d34bSNobuhiro Iwamatsu #include <common.h> 12e525d34bSNobuhiro Iwamatsu #include <malloc.h> 13e525d34bSNobuhiro Iwamatsu #include <netdev.h> 14e525d34bSNobuhiro Iwamatsu #include <dm.h> 15e525d34bSNobuhiro Iwamatsu #include <dm/platform_data/serial_sh.h> 16e525d34bSNobuhiro Iwamatsu #include <asm/processor.h> 17e525d34bSNobuhiro Iwamatsu #include <asm/mach-types.h> 18e525d34bSNobuhiro Iwamatsu #include <asm/io.h> 191221ce45SMasahiro Yamada #include <linux/errno.h> 20e525d34bSNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 21e525d34bSNobuhiro Iwamatsu #include <asm/gpio.h> 22e525d34bSNobuhiro Iwamatsu #include <asm/arch/gpio.h> 23e525d34bSNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 24e525d34bSNobuhiro Iwamatsu #include <asm/arch/rcar-mstp.h> 2550fb0c45SMarek Vasut #include <asm/arch/sh_sdhi.h> 26e525d34bSNobuhiro Iwamatsu #include <i2c.h> 27e525d34bSNobuhiro Iwamatsu #include <mmc.h> 28e525d34bSNobuhiro Iwamatsu 29e525d34bSNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 30e525d34bSNobuhiro Iwamatsu 31e525d34bSNobuhiro Iwamatsu #define CPGWPCR 0xE6150904 32e525d34bSNobuhiro Iwamatsu #define CPGWPR 0xE615090C 33e525d34bSNobuhiro Iwamatsu 34e525d34bSNobuhiro Iwamatsu #define CLK2MHZ(clk) (clk / 1000 / 1000) 35e525d34bSNobuhiro Iwamatsu void s_init(void) 36e525d34bSNobuhiro Iwamatsu { 37e525d34bSNobuhiro Iwamatsu struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 38e525d34bSNobuhiro Iwamatsu struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 39e525d34bSNobuhiro Iwamatsu 40e525d34bSNobuhiro Iwamatsu /* Watchdog init */ 41e525d34bSNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 42e525d34bSNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 43e525d34bSNobuhiro Iwamatsu 44e525d34bSNobuhiro Iwamatsu writel(0xA5A50000, CPGWPCR); 45e525d34bSNobuhiro Iwamatsu writel(0xFFFFFFFF, CPGWPR); 46e525d34bSNobuhiro Iwamatsu } 47e525d34bSNobuhiro Iwamatsu 48ae7a74a6SMarek Vasut #define GSX_MSTP112 BIT(12) /* 3DG */ 49ae7a74a6SMarek Vasut #define TMU0_MSTP125 BIT(25) /* secure */ 50ae7a74a6SMarek Vasut #define TMU1_MSTP124 BIT(24) /* non-secure */ 51ae7a74a6SMarek Vasut #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ 5290e53f8bSMarek Vasut #define ETHERAVB_MSTP812 BIT(12) 53fe2e8ff9SMarek Vasut #define DVFS_MSTP926 BIT(26) 5450fb0c45SMarek Vasut #define SD0_MSTP314 BIT(14) 5550fb0c45SMarek Vasut #define SD1_MSTP313 BIT(13) 5650fb0c45SMarek Vasut #define SD2_MSTP312 BIT(12) /* either MMC0 */ 5750fb0c45SMarek Vasut #define SD3_MSTP311 BIT(11) /* either MMC1 */ 5850fb0c45SMarek Vasut 5950fb0c45SMarek Vasut #define SD0CKCR 0xE6150074 6050fb0c45SMarek Vasut #define SD1CKCR 0xE6150078 6150fb0c45SMarek Vasut #define SD2CKCR 0xE6150268 6250fb0c45SMarek Vasut #define SD3CKCR 0xE615026C 63e525d34bSNobuhiro Iwamatsu 64e525d34bSNobuhiro Iwamatsu int board_early_init_f(void) 65e525d34bSNobuhiro Iwamatsu { 66e525d34bSNobuhiro Iwamatsu /* TMU0,1 */ /* which use ? */ 67e525d34bSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); 68e525d34bSNobuhiro Iwamatsu /* SCIF2 */ 69e525d34bSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); 7090e53f8bSMarek Vasut /* EHTERAVB */ 7190e53f8bSMarek Vasut mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); 7250fb0c45SMarek Vasut /* eMMC */ 7350fb0c45SMarek Vasut mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); 7450fb0c45SMarek Vasut /* SDHI0, 3 */ 7550fb0c45SMarek Vasut mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311); 7650fb0c45SMarek Vasut 7750fb0c45SMarek Vasut writel(0, SD0CKCR); 7850fb0c45SMarek Vasut writel(0, SD1CKCR); 7950fb0c45SMarek Vasut writel(0, SD2CKCR); 8050fb0c45SMarek Vasut writel(0, SD3CKCR); 81e525d34bSNobuhiro Iwamatsu 82fe2e8ff9SMarek Vasut #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) 83fe2e8ff9SMarek Vasut /* DVFS for reset */ 84fe2e8ff9SMarek Vasut mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); 85fe2e8ff9SMarek Vasut #endif 86e525d34bSNobuhiro Iwamatsu return 0; 87e525d34bSNobuhiro Iwamatsu } 88e525d34bSNobuhiro Iwamatsu 89e525d34bSNobuhiro Iwamatsu /* SYSC */ 90e525d34bSNobuhiro Iwamatsu /* R/- 32 Power status register 2(3DG) */ 91e525d34bSNobuhiro Iwamatsu #define SYSC_PWRSR2 0xE6180100 92e525d34bSNobuhiro Iwamatsu /* -/W 32 Power resume control register 2 (3DG) */ 93e525d34bSNobuhiro Iwamatsu #define SYSC_PWRONCR2 0xE618010C 94e525d34bSNobuhiro Iwamatsu 95e525d34bSNobuhiro Iwamatsu int board_init(void) 96e525d34bSNobuhiro Iwamatsu { 97e525d34bSNobuhiro Iwamatsu /* adress of boot parameters */ 98e525d34bSNobuhiro Iwamatsu gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; 99e525d34bSNobuhiro Iwamatsu 100e525d34bSNobuhiro Iwamatsu /* Init PFC controller */ 101e525d34bSNobuhiro Iwamatsu r8a7795_pinmux_init(); 102e525d34bSNobuhiro Iwamatsu 103e525d34bSNobuhiro Iwamatsu /* GSX: force power and clock supply */ 104e525d34bSNobuhiro Iwamatsu writel(0x0000001F, SYSC_PWRONCR2); 105e525d34bSNobuhiro Iwamatsu while (readl(SYSC_PWRSR2) != 0x000003E0) 106e525d34bSNobuhiro Iwamatsu mdelay(20); 107e525d34bSNobuhiro Iwamatsu 108e525d34bSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); 109e525d34bSNobuhiro Iwamatsu 110d1018f5fSMarek Vasut /* USB1 pull-up */ 111d1018f5fSMarek Vasut setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); 112d1018f5fSMarek Vasut 11390e53f8bSMarek Vasut #ifdef CONFIG_RAVB 11490e53f8bSMarek Vasut /* EtherAVB Enable */ 11590e53f8bSMarek Vasut /* GPSR2 */ 11690e53f8bSMarek Vasut gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); 11790e53f8bSMarek Vasut gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); 11890e53f8bSMarek Vasut gpio_request(GPIO_GFN_AVB_LINK, NULL); 11990e53f8bSMarek Vasut gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); 12090e53f8bSMarek Vasut gpio_request(GPIO_GFN_AVB_MAGIC, NULL); 12190e53f8bSMarek Vasut gpio_request(GPIO_GFN_AVB_MDC, NULL); 12290e53f8bSMarek Vasut 12390e53f8bSMarek Vasut /* IPSR0 */ 12490e53f8bSMarek Vasut gpio_request(GPIO_IFN_AVB_MDC, NULL); 12590e53f8bSMarek Vasut gpio_request(GPIO_IFN_AVB_MAGIC, NULL); 12690e53f8bSMarek Vasut gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); 12790e53f8bSMarek Vasut gpio_request(GPIO_IFN_AVB_LINK, NULL); 12890e53f8bSMarek Vasut gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); 12990e53f8bSMarek Vasut gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); 13090e53f8bSMarek Vasut /* IPSR1 */ 13190e53f8bSMarek Vasut gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); 13290e53f8bSMarek Vasut /* IPSR2 */ 13390e53f8bSMarek Vasut gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); 13490e53f8bSMarek Vasut /* IPSR3 */ 13590e53f8bSMarek Vasut gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); 13690e53f8bSMarek Vasut 137d1018f5fSMarek Vasut /* USB2_OVC */ 138d1018f5fSMarek Vasut gpio_request(GPIO_GP_6_15, NULL); 139d1018f5fSMarek Vasut gpio_direction_input(GPIO_GP_6_15); 140d1018f5fSMarek Vasut 141d1018f5fSMarek Vasut /* USB2_PWEN */ 142d1018f5fSMarek Vasut gpio_request(GPIO_GP_6_14, NULL); 143d1018f5fSMarek Vasut gpio_direction_output(GPIO_GP_6_14, 1); 144d1018f5fSMarek Vasut gpio_set_value(GPIO_GP_6_14, 1); 145d1018f5fSMarek Vasut 14690e53f8bSMarek Vasut /* AVB_PHY_RST */ 14790e53f8bSMarek Vasut gpio_request(GPIO_GP_2_10, NULL); 14890e53f8bSMarek Vasut gpio_direction_output(GPIO_GP_2_10, 0); 14990e53f8bSMarek Vasut mdelay(20); 15090e53f8bSMarek Vasut gpio_set_value(GPIO_GP_2_10, 1); 15190e53f8bSMarek Vasut udelay(1); 15290e53f8bSMarek Vasut #endif 15390e53f8bSMarek Vasut 154e525d34bSNobuhiro Iwamatsu return 0; 155e525d34bSNobuhiro Iwamatsu } 156e525d34bSNobuhiro Iwamatsu 15790e53f8bSMarek Vasut static struct eth_pdata salvator_x_ravb_platdata = { 15890e53f8bSMarek Vasut .iobase = 0xE6800000, 15990e53f8bSMarek Vasut .phy_interface = 0, 16090e53f8bSMarek Vasut .max_speed = 1000, 16190e53f8bSMarek Vasut }; 16290e53f8bSMarek Vasut 16390e53f8bSMarek Vasut U_BOOT_DEVICE(salvator_x_ravb) = { 16490e53f8bSMarek Vasut .name = "ravb", 16590e53f8bSMarek Vasut .platdata = &salvator_x_ravb_platdata, 16690e53f8bSMarek Vasut }; 16790e53f8bSMarek Vasut 16850fb0c45SMarek Vasut #ifdef CONFIG_SH_SDHI 16950fb0c45SMarek Vasut int board_mmc_init(bd_t *bis) 17050fb0c45SMarek Vasut { 17150fb0c45SMarek Vasut int ret = -ENODEV; 17250fb0c45SMarek Vasut 17350fb0c45SMarek Vasut /* SDHI0 */ 17450fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_DAT0, NULL); 17550fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_DAT1, NULL); 17650fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_DAT2, NULL); 17750fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_DAT3, NULL); 17850fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_CLK, NULL); 17950fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_CMD, NULL); 18050fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_CD, NULL); 18150fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD0_WP, NULL); 18250fb0c45SMarek Vasut 18350fb0c45SMarek Vasut gpio_request(GPIO_GP_5_2, NULL); 18450fb0c45SMarek Vasut gpio_request(GPIO_GP_5_1, NULL); 18550fb0c45SMarek Vasut gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ 18650fb0c45SMarek Vasut gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ 18750fb0c45SMarek Vasut 18850fb0c45SMarek Vasut ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 18950fb0c45SMarek Vasut SH_SDHI_QUIRK_64BIT_BUF); 19050fb0c45SMarek Vasut if (ret) 19150fb0c45SMarek Vasut return ret; 19250fb0c45SMarek Vasut 19350fb0c45SMarek Vasut /* SDHI1/SDHI2 eMMC */ 19450fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD1_DAT0, NULL); 19550fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD1_DAT1, NULL); 19650fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD1_DAT2, NULL); 19750fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD1_DAT3, NULL); 19850fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD2_DAT0, NULL); 19950fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD2_DAT1, NULL); 20050fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD2_DAT2, NULL); 20150fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD2_DAT3, NULL); 20250fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD2_CLK, NULL); 20350fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD2_CMD, NULL); 20450fb0c45SMarek Vasut gpio_request(GPIO_GP_5_3, NULL); 20550fb0c45SMarek Vasut gpio_request(GPIO_GP_5_9, NULL); 20650fb0c45SMarek Vasut gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ 20750fb0c45SMarek Vasut gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ 20850fb0c45SMarek Vasut 20950fb0c45SMarek Vasut ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1, 21050fb0c45SMarek Vasut SH_SDHI_QUIRK_64BIT_BUF); 21150fb0c45SMarek Vasut if (ret) 21250fb0c45SMarek Vasut return ret; 21350fb0c45SMarek Vasut 21450fb0c45SMarek Vasut /* SDHI3 */ 21550fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */ 21650fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */ 21750fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */ 21850fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */ 21950fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */ 22050fb0c45SMarek Vasut gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */ 22150fb0c45SMarek Vasut /* IPSR10 */ 22250fb0c45SMarek Vasut gpio_request(GPIO_FN_SD3_CD, NULL); 22350fb0c45SMarek Vasut gpio_request(GPIO_FN_SD3_WP, NULL); 22450fb0c45SMarek Vasut 22550fb0c45SMarek Vasut gpio_request(GPIO_GP_3_15, NULL); 22650fb0c45SMarek Vasut gpio_request(GPIO_GP_3_14, NULL); 22750fb0c45SMarek Vasut gpio_direction_output(GPIO_GP_3_15, 1); /* power on */ 22850fb0c45SMarek Vasut gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */ 22950fb0c45SMarek Vasut 23050fb0c45SMarek Vasut ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2, 23150fb0c45SMarek Vasut SH_SDHI_QUIRK_64BIT_BUF); 23250fb0c45SMarek Vasut return ret; 23350fb0c45SMarek Vasut } 23450fb0c45SMarek Vasut #endif 23550fb0c45SMarek Vasut 236e525d34bSNobuhiro Iwamatsu int dram_init(void) 237e525d34bSNobuhiro Iwamatsu { 238*8f284e66SMarek Vasut gd->ram_size = PHYS_SDRAM_1_SIZE; 239*8f284e66SMarek Vasut #if (CONFIG_NR_DRAM_BANKS >= 2) 240*8f284e66SMarek Vasut gd->ram_size += PHYS_SDRAM_2_SIZE; 241*8f284e66SMarek Vasut #endif 242*8f284e66SMarek Vasut #if (CONFIG_NR_DRAM_BANKS >= 3) 243*8f284e66SMarek Vasut gd->ram_size += PHYS_SDRAM_3_SIZE; 244*8f284e66SMarek Vasut #endif 245*8f284e66SMarek Vasut #if (CONFIG_NR_DRAM_BANKS >= 4) 246*8f284e66SMarek Vasut gd->ram_size += PHYS_SDRAM_4_SIZE; 247*8f284e66SMarek Vasut #endif 248e525d34bSNobuhiro Iwamatsu 249e525d34bSNobuhiro Iwamatsu return 0; 250e525d34bSNobuhiro Iwamatsu } 251e525d34bSNobuhiro Iwamatsu 252*8f284e66SMarek Vasut int dram_init_banksize(void) 253*8f284e66SMarek Vasut { 254*8f284e66SMarek Vasut gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 255*8f284e66SMarek Vasut gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 256*8f284e66SMarek Vasut #if (CONFIG_NR_DRAM_BANKS >= 2) 257*8f284e66SMarek Vasut gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 258*8f284e66SMarek Vasut gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 259*8f284e66SMarek Vasut #endif 260*8f284e66SMarek Vasut #if (CONFIG_NR_DRAM_BANKS >= 3) 261*8f284e66SMarek Vasut gd->bd->bi_dram[2].start = PHYS_SDRAM_3; 262*8f284e66SMarek Vasut gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; 263*8f284e66SMarek Vasut #endif 264*8f284e66SMarek Vasut #if (CONFIG_NR_DRAM_BANKS >= 4) 265*8f284e66SMarek Vasut gd->bd->bi_dram[3].start = PHYS_SDRAM_4; 266*8f284e66SMarek Vasut gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; 267*8f284e66SMarek Vasut #endif 268*8f284e66SMarek Vasut return 0; 269*8f284e66SMarek Vasut } 270*8f284e66SMarek Vasut 271e525d34bSNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 272e525d34bSNobuhiro Iwamatsu CONFIG_RCAR_BOARD_STRING 273e525d34bSNobuhiro Iwamatsu }; 274e525d34bSNobuhiro Iwamatsu 275e525d34bSNobuhiro Iwamatsu #define RST_BASE 0xE6160000 276e525d34bSNobuhiro Iwamatsu #define RST_CA57RESCNT (RST_BASE + 0x40) 277e525d34bSNobuhiro Iwamatsu #define RST_CA53RESCNT (RST_BASE + 0x44) 278e525d34bSNobuhiro Iwamatsu #define RST_RSTOUTCR (RST_BASE + 0x58) 279e525d34bSNobuhiro Iwamatsu #define RST_CODE 0xA5A5000F 280e525d34bSNobuhiro Iwamatsu 281e525d34bSNobuhiro Iwamatsu void reset_cpu(ulong addr) 282e525d34bSNobuhiro Iwamatsu { 283fe2e8ff9SMarek Vasut #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) 284fe2e8ff9SMarek Vasut i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); 285fe2e8ff9SMarek Vasut #else 286e525d34bSNobuhiro Iwamatsu /* only CA57 ? */ 287e525d34bSNobuhiro Iwamatsu writel(RST_CODE, RST_CA57RESCNT); 288fe2e8ff9SMarek Vasut #endif 289e525d34bSNobuhiro Iwamatsu } 290e525d34bSNobuhiro Iwamatsu 291e525d34bSNobuhiro Iwamatsu static const struct sh_serial_platdata serial_platdata = { 292e525d34bSNobuhiro Iwamatsu .base = SCIF2_BASE, 293e525d34bSNobuhiro Iwamatsu .type = PORT_SCIF, 2948474681cSMarek Vasut .clk = CONFIG_SH_SCIF_CLK_FREQ, 2958474681cSMarek Vasut .clk_mode = INT_CLK, 296e525d34bSNobuhiro Iwamatsu }; 297e525d34bSNobuhiro Iwamatsu 298e525d34bSNobuhiro Iwamatsu U_BOOT_DEVICE(salvator_x_scif2) = { 299e525d34bSNobuhiro Iwamatsu .name = "serial_sh", 300e525d34bSNobuhiro Iwamatsu .platdata = &serial_platdata, 301e525d34bSNobuhiro Iwamatsu }; 302