1e525d34bSNobuhiro Iwamatsu /* 2e525d34bSNobuhiro Iwamatsu * board/renesas/salvator-x/salvator-x.c 3e525d34bSNobuhiro Iwamatsu * This file is Salvator-X board support. 4e525d34bSNobuhiro Iwamatsu * 5e525d34bSNobuhiro Iwamatsu * Copyright (C) 2015 Renesas Electronics Corporation 6e525d34bSNobuhiro Iwamatsu * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 7e525d34bSNobuhiro Iwamatsu * 8e525d34bSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0+ 9e525d34bSNobuhiro Iwamatsu */ 10e525d34bSNobuhiro Iwamatsu 11e525d34bSNobuhiro Iwamatsu #include <common.h> 12e525d34bSNobuhiro Iwamatsu #include <malloc.h> 13e525d34bSNobuhiro Iwamatsu #include <netdev.h> 14e525d34bSNobuhiro Iwamatsu #include <dm.h> 15e525d34bSNobuhiro Iwamatsu #include <dm/platform_data/serial_sh.h> 16e525d34bSNobuhiro Iwamatsu #include <asm/processor.h> 17e525d34bSNobuhiro Iwamatsu #include <asm/mach-types.h> 18e525d34bSNobuhiro Iwamatsu #include <asm/io.h> 191221ce45SMasahiro Yamada #include <linux/errno.h> 20e525d34bSNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 21e525d34bSNobuhiro Iwamatsu #include <asm/gpio.h> 22e525d34bSNobuhiro Iwamatsu #include <asm/arch/gpio.h> 23e525d34bSNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 24e525d34bSNobuhiro Iwamatsu #include <asm/arch/rcar-mstp.h> 25e525d34bSNobuhiro Iwamatsu #include <i2c.h> 26e525d34bSNobuhiro Iwamatsu #include <mmc.h> 27e525d34bSNobuhiro Iwamatsu 28e525d34bSNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 29e525d34bSNobuhiro Iwamatsu 30e525d34bSNobuhiro Iwamatsu #define CPGWPCR 0xE6150904 31e525d34bSNobuhiro Iwamatsu #define CPGWPR 0xE615090C 32e525d34bSNobuhiro Iwamatsu 33e525d34bSNobuhiro Iwamatsu #define CLK2MHZ(clk) (clk / 1000 / 1000) 34e525d34bSNobuhiro Iwamatsu void s_init(void) 35e525d34bSNobuhiro Iwamatsu { 36e525d34bSNobuhiro Iwamatsu struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 37e525d34bSNobuhiro Iwamatsu struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 38e525d34bSNobuhiro Iwamatsu 39e525d34bSNobuhiro Iwamatsu /* Watchdog init */ 40e525d34bSNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 41e525d34bSNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 42e525d34bSNobuhiro Iwamatsu 43e525d34bSNobuhiro Iwamatsu writel(0xA5A50000, CPGWPCR); 44e525d34bSNobuhiro Iwamatsu writel(0xFFFFFFFF, CPGWPR); 45e525d34bSNobuhiro Iwamatsu } 46e525d34bSNobuhiro Iwamatsu 47ae7a74a6SMarek Vasut #define GSX_MSTP112 BIT(12) /* 3DG */ 48ae7a74a6SMarek Vasut #define TMU0_MSTP125 BIT(25) /* secure */ 49ae7a74a6SMarek Vasut #define TMU1_MSTP124 BIT(24) /* non-secure */ 50ae7a74a6SMarek Vasut #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ 51e525d34bSNobuhiro Iwamatsu 52e525d34bSNobuhiro Iwamatsu int board_early_init_f(void) 53e525d34bSNobuhiro Iwamatsu { 54e525d34bSNobuhiro Iwamatsu /* TMU0,1 */ /* which use ? */ 55e525d34bSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); 56e525d34bSNobuhiro Iwamatsu /* SCIF2 */ 57e525d34bSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); 58e525d34bSNobuhiro Iwamatsu 59e525d34bSNobuhiro Iwamatsu return 0; 60e525d34bSNobuhiro Iwamatsu } 61e525d34bSNobuhiro Iwamatsu 62e525d34bSNobuhiro Iwamatsu /* SYSC */ 63e525d34bSNobuhiro Iwamatsu /* R/- 32 Power status register 2(3DG) */ 64e525d34bSNobuhiro Iwamatsu #define SYSC_PWRSR2 0xE6180100 65e525d34bSNobuhiro Iwamatsu /* -/W 32 Power resume control register 2 (3DG) */ 66e525d34bSNobuhiro Iwamatsu #define SYSC_PWRONCR2 0xE618010C 67e525d34bSNobuhiro Iwamatsu 68e525d34bSNobuhiro Iwamatsu int board_init(void) 69e525d34bSNobuhiro Iwamatsu { 70e525d34bSNobuhiro Iwamatsu /* adress of boot parameters */ 71e525d34bSNobuhiro Iwamatsu gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; 72e525d34bSNobuhiro Iwamatsu 73e525d34bSNobuhiro Iwamatsu /* Init PFC controller */ 74e525d34bSNobuhiro Iwamatsu r8a7795_pinmux_init(); 75e525d34bSNobuhiro Iwamatsu 76e525d34bSNobuhiro Iwamatsu /* GSX: force power and clock supply */ 77e525d34bSNobuhiro Iwamatsu writel(0x0000001F, SYSC_PWRONCR2); 78e525d34bSNobuhiro Iwamatsu while (readl(SYSC_PWRSR2) != 0x000003E0) 79e525d34bSNobuhiro Iwamatsu mdelay(20); 80e525d34bSNobuhiro Iwamatsu 81e525d34bSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); 82e525d34bSNobuhiro Iwamatsu 83e525d34bSNobuhiro Iwamatsu return 0; 84e525d34bSNobuhiro Iwamatsu } 85e525d34bSNobuhiro Iwamatsu 86e525d34bSNobuhiro Iwamatsu int dram_init(void) 87e525d34bSNobuhiro Iwamatsu { 88e525d34bSNobuhiro Iwamatsu gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 89e525d34bSNobuhiro Iwamatsu 90e525d34bSNobuhiro Iwamatsu return 0; 91e525d34bSNobuhiro Iwamatsu } 92e525d34bSNobuhiro Iwamatsu 93e525d34bSNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 94e525d34bSNobuhiro Iwamatsu CONFIG_RCAR_BOARD_STRING 95e525d34bSNobuhiro Iwamatsu }; 96e525d34bSNobuhiro Iwamatsu 97e525d34bSNobuhiro Iwamatsu #define RST_BASE 0xE6160000 98e525d34bSNobuhiro Iwamatsu #define RST_CA57RESCNT (RST_BASE + 0x40) 99e525d34bSNobuhiro Iwamatsu #define RST_CA53RESCNT (RST_BASE + 0x44) 100e525d34bSNobuhiro Iwamatsu #define RST_RSTOUTCR (RST_BASE + 0x58) 101e525d34bSNobuhiro Iwamatsu #define RST_CODE 0xA5A5000F 102e525d34bSNobuhiro Iwamatsu 103e525d34bSNobuhiro Iwamatsu void reset_cpu(ulong addr) 104e525d34bSNobuhiro Iwamatsu { 105e525d34bSNobuhiro Iwamatsu /* only CA57 ? */ 106e525d34bSNobuhiro Iwamatsu writel(RST_CODE, RST_CA57RESCNT); 107e525d34bSNobuhiro Iwamatsu } 108e525d34bSNobuhiro Iwamatsu 109e525d34bSNobuhiro Iwamatsu static const struct sh_serial_platdata serial_platdata = { 110e525d34bSNobuhiro Iwamatsu .base = SCIF2_BASE, 111e525d34bSNobuhiro Iwamatsu .type = PORT_SCIF, 112*8474681cSMarek Vasut .clk = CONFIG_SH_SCIF_CLK_FREQ, 113*8474681cSMarek Vasut .clk_mode = INT_CLK, 114e525d34bSNobuhiro Iwamatsu }; 115e525d34bSNobuhiro Iwamatsu 116e525d34bSNobuhiro Iwamatsu U_BOOT_DEVICE(salvator_x_scif2) = { 117e525d34bSNobuhiro Iwamatsu .name = "serial_sh", 118e525d34bSNobuhiro Iwamatsu .platdata = &serial_platdata, 119e525d34bSNobuhiro Iwamatsu }; 120