1/*
2 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
3 * Copyright (C) 2012 Phil Edworthy
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 *
7 * Based on board/renesas/rsk7264/lowlevel_init.S
8 *
9 * SPDX-License-Identifier:	GPL-2.0+
10 */
11#include <config.h>
12
13#include <asm/processor.h>
14#include <asm/macro.h>
15
16	.global	lowlevel_init
17
18	.text
19	.align	2
20
21lowlevel_init:
22	/* Flush and enable caches (data cache in write-through mode) */
23	write32	CCR1_A ,CCR1_D
24
25	/* Disable WDT */
26	write16	WTCSR_A, WTCSR_D
27	write16	WTCNT_A, WTCNT_D
28
29	/* Disable Register Bank interrupts */
30	write16 IBNR_A, IBNR_D
31
32	/* Set clocks based on 13.225MHz xtal */
33	write16	FRQCR_A, FRQCR_D	/* CPU=266MHz, I=133MHz, P=66MHz */
34
35	/* Enable all peripherals */
36	write8 STBCR3_A, STBCR3_D
37	write8 STBCR4_A, STBCR4_D
38	write8 STBCR5_A, STBCR5_D
39	write8 STBCR6_A, STBCR6_D
40	write8 STBCR7_A, STBCR7_D
41	write8 STBCR8_A, STBCR8_D
42	write8 STBCR9_A, STBCR9_D
43	write8 STBCR10_A, STBCR10_D
44
45	/* SCIF7 and IIC2 */
46	write16 PJCR3_A, PJCR3_D	/* TXD7 */
47	write16 PECR1_A, PECR1_D	/* RXD7, SDA2, SCL2 */
48
49	/* Configure bus (CS0) */
50	write16 PFCR3_A, PFCR3_D	/* A24 */
51	write16 PFCR2_A, PFCR2_D	/* A23 and CS1# */
52	write16 PBCR5_A, PBCR5_D	/* A22, A21, A20 */
53	write16 PCCR0_A, PCCR0_D	/* DQMLL#, RD/WR# */
54	write32 CS0WCR_A, CS0WCR_D
55	write32 CS0BCR_A, CS0BCR_D
56
57	/* Configure SDRAM (CS3) */
58	write16 PCCR2_A, PCCR2_D	/* CS3# */
59	write16 PCCR1_A, PCCR1_D	/* CKE, CAS#, RAS#, DQMLU# */
60	write16 PCCR0_A, PCCR0_D	/* DQMLL#, RD/WR# */
61	write32	CS3BCR_A, CS3BCR_D
62	write32	CS3WCR_A, CS3WCR_D
63	write32	SDCR_A, SDCR_D
64	write32	RTCOR_A, RTCOR_D
65	write32	RTCSR_A, RTCSR_D
66
67	/* Configure ethernet (CS1) */
68	write16 PHCR1_A, PHCR1_D	/* PINT5 on PH5 */
69	write16 PHCR0_A, PHCR0_D
70	write16 PFCR2_A, PFCR2_D	/* CS1# */
71	write32	CS1BCR_A, CS1BCR_D	/* Big endian */
72	write32	CS1WCR_A, CS1WCR_D	/* 1 cycle */
73	write16 PJDR1_A, PJDR1_D	/* FIFO-SEL = 1 */
74	write16 PJIOR1_A, PJIOR1_D
75
76	/* wait 200us */
77	mov.l	REPEAT_D, r3
78	mov	#0, r2
79repeat0:
80	add	#1, r2
81	cmp/hs	r3, r2
82	bf	repeat0
83	nop
84
85	mov.l	SDRAM_MODE, r1
86	mov	#0, r0
87	mov.l	r0, @r1
88
89	nop
90	rts
91
92	.align 4
93
94CCR1_A:		.long CCR1
95CCR1_D:		.long 0x0000090B
96
97STBCR3_A:	.long 0xFFFE0408
98STBCR4_A:	.long 0xFFFE040C
99STBCR5_A:	.long 0xFFFE0410
100STBCR6_A:	.long 0xFFFE0414
101STBCR7_A:	.long 0xFFFE0418
102STBCR8_A:	.long 0xFFFE041C
103STBCR9_A:	.long 0xFFFE0440
104STBCR10_A:	.long 0xFFFE0444
105STBCR3_D:	.long 0x0000001A
106STBCR4_D:	.long 0x00000000
107STBCR5_D:	.long 0x00000000
108STBCR6_D:	.long 0x00000000
109STBCR7_D:	.long 0x00000012
110STBCR8_D:	.long 0x00000009
111STBCR9_D:	.long 0x00000000
112STBCR10_D:	.long 0x00000010
113
114WTCSR_A:	.long 0xFFFE0000
115WTCNT_A:	.long 0xFFFE0002
116WTCSR_D:	.word 0xA518
117WTCNT_D:	.word 0x5A00
118
119IBNR_A:		.long 0xFFFE080E
120IBNR_D:		.word 0x0000
121.align 2
122FRQCR_A:	.long 0xFFFE0010
123FRQCR_D:	.word 0x0015
124.align 2
125
126PJCR3_A:	.long 0xFFFE3908
127PJCR3_D:	.word 0x5000
128.align 2
129PECR1_A:	.long 0xFFFE388C
130PECR1_D:	.word 0x2011
131.align 2
132
133PFCR3_A:	.long 0xFFFE38A8
134PFCR2_A:	.long 0xFFFE38AA
135PBCR5_A:	.long 0xFFFE3824
136PFCR3_D:	.word 0x0010
137PFCR2_D:	.word 0x0101
138PBCR5_D:	.word 0x0111
139.align 2
140CS0WCR_A:	.long 0xFFFC0028
141CS0WCR_D:	.long 0x00000341
142CS0BCR_A:	.long 0xFFFC0004
143CS0BCR_D:	.long 0x00000400
144
145PCCR2_A:	.long 0xFFFE384A
146PCCR1_A:	.long 0xFFFE384C
147PCCR0_A:	.long 0xFFFE384E
148PCCR2_D:	.word 0x0001
149PCCR1_D:	.word 0x1111
150PCCR0_D:	.word 0x1111
151.align 2
152CS3BCR_A:	.long 0xFFFC0010
153CS3BCR_D:	.long 0x00004400
154CS3WCR_A:	.long 0xFFFC0034
155CS3WCR_D:	.long 0x00004912
156SDCR_A:		.long 0xFFFC004C
157SDCR_D:		.long 0x00000811
158RTCOR_A:	.long 0xFFFC0058
159RTCOR_D:	.long 0xA55A0035
160RTCSR_A:	.long 0xFFFC0050
161RTCSR_D:	.long 0xA55A0010
162.align 2
163SDRAM_MODE:	.long 0xFFFC5460
164REPEAT_D:	.long 0x000033F1
165
166PHCR1_A:	.long 0xFFFE38EC
167PHCR0_A:	.long 0xFFFE38EE
168PHCR1_D:	.word 0x2222
169PHCR0_D:	.word 0x2222
170.align 2
171CS1BCR_A:	.long 0xFFFC0008
172CS1BCR_D:	.long 0x00000400
173CS1WCR_A:	.long 0xFFFC002C
174CS1WCR_D:	.long 0x00000080
175PJDR1_A:	.long 0xFFFE3914
176PJDR1_D:	.word 0x0000
177.align 2
178PJIOR1_A:	.long 0xFFFE3910
179PJIOR1_D:	.word 0x8000
180.align 2
181