1/*
2 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
3 * Copyright (C) 2012 Phil Edworthy
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 *
7 * Based on board/renesas/rsk7264/lowlevel_init.S
8 *
9 * This file is released under the terms of GPL v2 and any later version.
10 * See the file COPYING in the root directory of the source tree for details.
11 */
12#include <config.h>
13#include <version.h>
14
15#include <asm/processor.h>
16#include <asm/macro.h>
17
18	.global	lowlevel_init
19
20	.text
21	.align	2
22
23lowlevel_init:
24	/* Flush and enable caches (data cache in write-through mode) */
25	write32	CCR1_A ,CCR1_D
26
27	/* Disable WDT */
28	write16	WTCSR_A, WTCSR_D
29	write16	WTCNT_A, WTCNT_D
30
31	/* Disable Register Bank interrupts */
32	write16 IBNR_A, IBNR_D
33
34	/* Set clocks based on 13.225MHz xtal */
35	write16	FRQCR_A, FRQCR_D	/* CPU=266MHz, I=133MHz, P=66MHz */
36
37	/* Enable all peripherals */
38	write8 STBCR3_A, STBCR3_D
39	write8 STBCR4_A, STBCR4_D
40	write8 STBCR5_A, STBCR5_D
41	write8 STBCR6_A, STBCR6_D
42	write8 STBCR7_A, STBCR7_D
43	write8 STBCR8_A, STBCR8_D
44	write8 STBCR9_A, STBCR9_D
45	write8 STBCR10_A, STBCR10_D
46
47	/* SCIF7 and IIC2 */
48	write16 PJCR3_A, PJCR3_D	/* TXD7 */
49	write16 PECR1_A, PECR1_D	/* RXD7, SDA2, SCL2 */
50
51	/* Configure bus (CS0) */
52	write16 PFCR3_A, PFCR3_D	/* A24 */
53	write16 PFCR2_A, PFCR2_D	/* A23 and CS1# */
54	write16 PBCR5_A, PBCR5_D	/* A22, A21, A20 */
55	write16 PCCR0_A, PCCR0_D	/* DQMLL#, RD/WR# */
56	write32 CS0WCR_A, CS0WCR_D
57	write32 CS0BCR_A, CS0BCR_D
58
59	/* Configure SDRAM (CS3) */
60	write16 PCCR2_A, PCCR2_D	/* CS3# */
61	write16 PCCR1_A, PCCR1_D	/* CKE, CAS#, RAS#, DQMLU# */
62	write16 PCCR0_A, PCCR0_D	/* DQMLL#, RD/WR# */
63	write32	CS3BCR_A, CS3BCR_D
64	write32	CS3WCR_A, CS3WCR_D
65	write32	SDCR_A, SDCR_D
66	write32	RTCOR_A, RTCOR_D
67	write32	RTCSR_A, RTCSR_D
68
69	/* Configure ethernet (CS1) */
70	write16 PHCR1_A, PHCR1_D	/* PINT5 on PH5 */
71	write16 PHCR0_A, PHCR0_D
72	write16 PFCR2_A, PFCR2_D	/* CS1# */
73	write32	CS1BCR_A, CS1BCR_D	/* Big endian */
74	write32	CS1WCR_A, CS1WCR_D	/* 1 cycle */
75	write16 PJDR1_A, PJDR1_D	/* FIFO-SEL = 1 */
76	write16 PJIOR1_A, PJIOR1_D
77
78	/* wait 200us */
79	mov.l	REPEAT_D, r3
80	mov	#0, r2
81repeat0:
82	add	#1, r2
83	cmp/hs	r3, r2
84	bf	repeat0
85	nop
86
87	mov.l	SDRAM_MODE, r1
88	mov	#0, r0
89	mov.l	r0, @r1
90
91	nop
92	rts
93
94	.align 4
95
96CCR1_A:		.long CCR1
97CCR1_D:		.long 0x0000090B
98
99STBCR3_A:	.long 0xFFFE0408
100STBCR4_A:	.long 0xFFFE040C
101STBCR5_A:	.long 0xFFFE0410
102STBCR6_A:	.long 0xFFFE0414
103STBCR7_A:	.long 0xFFFE0418
104STBCR8_A:	.long 0xFFFE041C
105STBCR9_A:	.long 0xFFFE0440
106STBCR10_A:	.long 0xFFFE0444
107STBCR3_D:	.long 0x0000001A
108STBCR4_D:	.long 0x00000000
109STBCR5_D:	.long 0x00000000
110STBCR6_D:	.long 0x00000000
111STBCR7_D:	.long 0x00000012
112STBCR8_D:	.long 0x00000009
113STBCR9_D:	.long 0x00000000
114STBCR10_D:	.long 0x00000010
115
116WTCSR_A:	.long 0xFFFE0000
117WTCNT_A:	.long 0xFFFE0002
118WTCSR_D:	.word 0xA518
119WTCNT_D:	.word 0x5A00
120
121IBNR_A:		.long 0xFFFE080E
122IBNR_D:		.word 0x0000
123.align 2
124FRQCR_A:	.long 0xFFFE0010
125FRQCR_D:	.word 0x0015
126.align 2
127
128PJCR3_A:	.long 0xFFFE3908
129PJCR3_D:	.word 0x5000
130.align 2
131PECR1_A:	.long 0xFFFE388C
132PECR1_D:	.word 0x2011
133.align 2
134
135PFCR3_A:	.long 0xFFFE38A8
136PFCR2_A:	.long 0xFFFE38AA
137PBCR5_A:	.long 0xFFFE3824
138PFCR3_D:	.word 0x0010
139PFCR2_D:	.word 0x0101
140PBCR5_D:	.word 0x0111
141.align 2
142CS0WCR_A:	.long 0xFFFC0028
143CS0WCR_D:	.long 0x00000341
144CS0BCR_A:	.long 0xFFFC0004
145CS0BCR_D:	.long 0x00000400
146
147PCCR2_A:	.long 0xFFFE384A
148PCCR1_A:	.long 0xFFFE384C
149PCCR0_A:	.long 0xFFFE384E
150PCCR2_D:	.word 0x0001
151PCCR1_D:	.word 0x1111
152PCCR0_D:	.word 0x1111
153.align 2
154CS3BCR_A:	.long 0xFFFC0010
155CS3BCR_D:	.long 0x00004400
156CS3WCR_A:	.long 0xFFFC0034
157CS3WCR_D:	.long 0x00004912
158SDCR_A:		.long 0xFFFC004C
159SDCR_D:		.long 0x00000811
160RTCOR_A:	.long 0xFFFC0058
161RTCOR_D:	.long 0xA55A0035
162RTCSR_A:	.long 0xFFFC0050
163RTCSR_D:	.long 0xA55A0010
164.align 2
165SDRAM_MODE:	.long 0xFFFC5460
166REPEAT_D:	.long 0x000033F1
167
168PHCR1_A:	.long 0xFFFE38EC
169PHCR0_A:	.long 0xFFFE38EE
170PHCR1_D:	.word 0x2222
171PHCR0_D:	.word 0x2222
172.align 2
173CS1BCR_A:	.long 0xFFFC0008
174CS1BCR_D:	.long 0x00000400
175CS1WCR_A:	.long 0xFFFC002C
176CS1WCR_D:	.long 0x00000080
177PJDR1_A:	.long 0xFFFE3914
178PJDR1_D:	.word 0x0000
179.align 2
180PJIOR1_A:	.long 0xFFFE3910
181PJIOR1_D:	.word 0x8000
182.align 2
183