1/* 2 * Copyright (C) 2011 Renesas Electronics Europe Ltd. 3 * Copyright (C) 2008 Renesas Solutions Corp. 4 * Copyright (C) 2008 Nobuhiro Iwamatsu 5 * 6 * Based on board/renesas/rsk7203/lowlevel_init.S 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10#include <config.h> 11#include <version.h> 12 13#include <asm/processor.h> 14#include <asm/macro.h> 15 16 .global lowlevel_init 17 18 .text 19 .align 2 20 21lowlevel_init: 22 /* Cache setting */ 23 write32 CCR1_A ,CCR1_D 24 25 /* io_set_cpg */ 26 write8 STBCR3_A, STBCR3_D 27 write8 STBCR4_A, STBCR4_D 28 write8 STBCR5_A, STBCR5_D 29 write8 STBCR6_A, STBCR6_D 30 write8 STBCR7_A, STBCR7_D 31 write8 STBCR8_A, STBCR8_D 32 33 /* ConfigurePortPins */ 34 35 /* Leaving LED1 ON for sanity test */ 36 write16 PJCR1_A, PJCR1_D1 37 write16 PJCR2_A, PJCR2_D 38 write16 PJIOR0_A, PJIOR0_D1 39 write16 PJDR0_A, PJDR0_D 40 write16 PJPR0_A, PJPR0_D 41 42 /* Configure EN_PIN & RS_PIN */ 43 write16 PGCR2_A, PGCR2_D 44 write16 PGIOR0_A, PGIOR0_D 45 46 /* Configure the port pins connected to UART */ 47 write16 PJCR1_A, PJCR1_D2 48 write16 PJIOR0_A, PJIOR0_D2 49 50 /* Configure Operating Frequency */ 51 write16 WTCSR_A, WTCSR_D0 52 write16 WTCSR_A, WTCSR_D1 53 write16 WTCNT_A, WTCNT_D 54 55 /* Control of RESBANK */ 56 write16 IBNR_A, IBNR_D 57 /* Enable SCIF3 module */ 58 write16 STBCR4_A, STBCR4_D 59 60 /* Set clock mode*/ 61 write16 FRQCR_A, FRQCR_D 62 63 /* Configure Bus And Memory */ 64init_bsc_cs0: 65 66pfc_settings: 67 write16 PCCR2_A, PCCR2_D 68 write16 PCCR1_A, PCCR1_D 69 write16 PCCR0_A, PCCR0_D 70 71 write16 PBCR0_A, PBCR0_D 72 write16 PBCR1_A, PBCR1_D 73 write16 PBCR2_A, PBCR2_D 74 write16 PBCR3_A, PBCR3_D 75 write16 PBCR4_A, PBCR4_D 76 write16 PBCR5_A, PBCR5_D 77 78 write16 PDCR0_A, PDCR0_D 79 write16 PDCR1_A, PDCR1_D 80 write16 PDCR2_A, PDCR2_D 81 write16 PDCR3_A, PDCR3_D 82 83 write32 CS0WCR_A, CS0WCR_D 84 write32 CS0BCR_A, CS0BCR_D 85 86init_bsc_cs2: 87 write16 PJCR0_A, PJCR0_D 88 write32 CS2WCR_A, CS2WCR_D 89 90init_sdram: 91 write32 CS3BCR_A, CS3BCR_D 92 write32 CS3WCR_A, CS3WCR_D 93 write32 SDCR_A, SDCR_D 94 write32 RTCOR_A, RTCOR_D 95 write32 RTCSR_A, RTCSR_D 96 97 /* wait 200us */ 98 mov.l REPEAT_D, r3 99 mov #0, r2 100repeat0: 101 add #1, r2 102 cmp/hs r3, r2 103 bf repeat0 104 nop 105 106 mov.l SDRAM_MODE, r1 107 mov #0, r0 108 mov.l r0, @r1 109 110 nop 111 rts 112 113 .align 4 114 115CCR1_A: .long CCR1 116CCR1_D: .long 0x0000090B 117FRQCR_A: .long 0xFFFE0010 118FRQCR_D: .word 0x1003 119.align 2 120STBCR3_A: .long 0xFFFE0408 121STBCR3_D: .long 0x00000002 122STBCR4_A: .long 0xFFFE040C 123STBCR4_D: .word 0x0000 124.align 2 125STBCR5_A: .long 0xFFFE0410 126STBCR5_D: .long 0x00000010 127STBCR6_A: .long 0xFFFE0414 128STBCR6_D: .long 0x00000002 129STBCR7_A: .long 0xFFFE0418 130STBCR7_D: .long 0x0000002A 131STBCR8_A: .long 0xFFFE041C 132STBCR8_D: .long 0x0000007E 133PJCR1_A: .long 0xFFFE390C 134PJCR1_D1: .word 0x0000 135PJCR1_D2: .word 0x0022 136PJCR2_A: .long 0xFFFE390A 137PJCR2_D: .word 0x0000 138.align 2 139PJIOR0_A: .long 0xFFFE3912 140PJIOR0_D1: .word 0x0FC0 141PJIOR0_D2: .word 0x0FE0 142PJDR0_A: .long 0xFFFE3916 143PJDR0_D: .word 0x0FBF 144.align 2 145PJPR0_A: .long 0xFFFE391A 146PJPR0_D: .long 0x00000FBF 147PGCR2_A: .long 0xFFFE38CA 148PGCR2_D: .word 0x0000 149.align 2 150PGIOR0_A: .long 0xFFFE38D2 151PGIOR0_D: .word 0x03F0 152.align 2 153WTCSR_A: .long 0xFFFE0000 154WTCSR_D0: .word 0x0000 155WTCSR_D1: .word 0x0000 156WTCNT_A: .long 0xFFFE0002 157WTCNT_D: .word 0x0000 158.align 2 159PCCR0_A: .long 0xFFFE384E 160PDCR0_A: .long 0xFFFE386E 161PDCR1_A: .long 0xFFFE386C 162PDCR2_A: .long 0xFFFE386A 163PDCR3_A: .long 0xFFFE3868 164PBCR0_A: .long 0xFFFE382E 165PBCR1_A: .long 0xFFFE382C 166PBCR2_A: .long 0xFFFE382A 167PBCR3_A: .long 0xFFFE3828 168PBCR4_A: .long 0xFFFE3826 169PBCR5_A: .long 0xFFFE3824 170PCCR0_D: .word 0x1111 171PDCR0_D: .word 0x1111 172PDCR1_D: .word 0x1111 173PDCR2_D: .word 0x1111 174PDCR3_D: .word 0x1111 175PBCR0_D: .word 0x1110 176PBCR1_D: .word 0x1111 177PBCR2_D: .word 0x1111 178PBCR3_D: .word 0x1111 179PBCR4_D: .word 0x1111 180PBCR5_D: .word 0x0111 181.align 2 182CS0WCR_A: .long 0xFFFC0028 183CS0WCR_D: .long 0x00000B41 184CS0BCR_A: .long 0xFFFC0004 185CS0BCR_D: .long 0x10000400 186PJCR0_A: .long 0xFFFE390E 187PJCR0_D: .word 0x3300 188.align 2 189CS2WCR_A: .long 0xFFFC0030 190CS2WCR_D: .long 0x00000B01 191PCCR2_A: .long 0xFFFE384A 192PCCR2_D: .word 0x0001 193.align 2 194PCCR1_A: .long 0xFFFE384C 195PCCR1_D: .word 0x1111 196.align 2 197CS3BCR_A: .long 0xFFFC0010 198CS3BCR_D: .long 0x00004400 199CS3WCR_A: .long 0xFFFC0034 200CS3WCR_D: .long 0x0000288A 201SDCR_A: .long 0xFFFC004C 202SDCR_D: .long 0x00000812 203RTCOR_A: .long 0xFFFC0058 204RTCOR_D: .long 0xA55A0046 205RTCSR_A: .long 0xFFFC0050 206RTCSR_D: .long 0xA55A0010 207IBNR_A: .long 0xFFFE080E 208IBNR_D: .word 0x0000 209.align 2 210SDRAM_MODE: .long 0xFFFC5040 211REPEAT_D: .long 0x00000085 212