1/* 2 * Copyright (C) 2011 Renesas Electronics Europe Ltd. 3 * Copyright (C) 2008 Renesas Solutions Corp. 4 * Copyright (C) 2008 Nobuhiro Iwamatsu 5 * 6 * Based on board/renesas/rsk7203/lowlevel_init.S 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10#include <config.h> 11 12#include <asm/processor.h> 13#include <asm/macro.h> 14 15 .global lowlevel_init 16 17 .text 18 .align 2 19 20lowlevel_init: 21 /* Cache setting */ 22 write32 CCR1_A ,CCR1_D 23 24 /* io_set_cpg */ 25 write8 STBCR3_A, STBCR3_D 26 write8 STBCR4_A, STBCR4_D 27 write8 STBCR5_A, STBCR5_D 28 write8 STBCR6_A, STBCR6_D 29 write8 STBCR7_A, STBCR7_D 30 write8 STBCR8_A, STBCR8_D 31 32 /* ConfigurePortPins */ 33 34 /* Leaving LED1 ON for sanity test */ 35 write16 PJCR1_A, PJCR1_D1 36 write16 PJCR2_A, PJCR2_D 37 write16 PJIOR0_A, PJIOR0_D1 38 write16 PJDR0_A, PJDR0_D 39 write16 PJPR0_A, PJPR0_D 40 41 /* Configure EN_PIN & RS_PIN */ 42 write16 PGCR2_A, PGCR2_D 43 write16 PGIOR0_A, PGIOR0_D 44 45 /* Configure the port pins connected to UART */ 46 write16 PJCR1_A, PJCR1_D2 47 write16 PJIOR0_A, PJIOR0_D2 48 49 /* Configure Operating Frequency */ 50 write16 WTCSR_A, WTCSR_D0 51 write16 WTCSR_A, WTCSR_D1 52 write16 WTCNT_A, WTCNT_D 53 54 /* Control of RESBANK */ 55 write16 IBNR_A, IBNR_D 56 /* Enable SCIF3 module */ 57 write16 STBCR4_A, STBCR4_D 58 59 /* Set clock mode*/ 60 write16 FRQCR_A, FRQCR_D 61 62 /* Configure Bus And Memory */ 63init_bsc_cs0: 64 65pfc_settings: 66 write16 PCCR2_A, PCCR2_D 67 write16 PCCR1_A, PCCR1_D 68 write16 PCCR0_A, PCCR0_D 69 70 write16 PBCR0_A, PBCR0_D 71 write16 PBCR1_A, PBCR1_D 72 write16 PBCR2_A, PBCR2_D 73 write16 PBCR3_A, PBCR3_D 74 write16 PBCR4_A, PBCR4_D 75 write16 PBCR5_A, PBCR5_D 76 77 write16 PDCR0_A, PDCR0_D 78 write16 PDCR1_A, PDCR1_D 79 write16 PDCR2_A, PDCR2_D 80 write16 PDCR3_A, PDCR3_D 81 82 write32 CS0WCR_A, CS0WCR_D 83 write32 CS0BCR_A, CS0BCR_D 84 85init_bsc_cs2: 86 write16 PJCR0_A, PJCR0_D 87 write32 CS2WCR_A, CS2WCR_D 88 89init_sdram: 90 write32 CS3BCR_A, CS3BCR_D 91 write32 CS3WCR_A, CS3WCR_D 92 write32 SDCR_A, SDCR_D 93 write32 RTCOR_A, RTCOR_D 94 write32 RTCSR_A, RTCSR_D 95 96 /* wait 200us */ 97 mov.l REPEAT_D, r3 98 mov #0, r2 99repeat0: 100 add #1, r2 101 cmp/hs r3, r2 102 bf repeat0 103 nop 104 105 mov.l SDRAM_MODE, r1 106 mov #0, r0 107 mov.l r0, @r1 108 109 nop 110 rts 111 112 .align 4 113 114CCR1_A: .long CCR1 115CCR1_D: .long 0x0000090B 116FRQCR_A: .long 0xFFFE0010 117FRQCR_D: .word 0x1003 118.align 2 119STBCR3_A: .long 0xFFFE0408 120STBCR3_D: .long 0x00000002 121STBCR4_A: .long 0xFFFE040C 122STBCR4_D: .word 0x0000 123.align 2 124STBCR5_A: .long 0xFFFE0410 125STBCR5_D: .long 0x00000010 126STBCR6_A: .long 0xFFFE0414 127STBCR6_D: .long 0x00000002 128STBCR7_A: .long 0xFFFE0418 129STBCR7_D: .long 0x0000002A 130STBCR8_A: .long 0xFFFE041C 131STBCR8_D: .long 0x0000007E 132PJCR1_A: .long 0xFFFE390C 133PJCR1_D1: .word 0x0000 134PJCR1_D2: .word 0x0022 135PJCR2_A: .long 0xFFFE390A 136PJCR2_D: .word 0x0000 137.align 2 138PJIOR0_A: .long 0xFFFE3912 139PJIOR0_D1: .word 0x0FC0 140PJIOR0_D2: .word 0x0FE0 141PJDR0_A: .long 0xFFFE3916 142PJDR0_D: .word 0x0FBF 143.align 2 144PJPR0_A: .long 0xFFFE391A 145PJPR0_D: .long 0x00000FBF 146PGCR2_A: .long 0xFFFE38CA 147PGCR2_D: .word 0x0000 148.align 2 149PGIOR0_A: .long 0xFFFE38D2 150PGIOR0_D: .word 0x03F0 151.align 2 152WTCSR_A: .long 0xFFFE0000 153WTCSR_D0: .word 0x0000 154WTCSR_D1: .word 0x0000 155WTCNT_A: .long 0xFFFE0002 156WTCNT_D: .word 0x0000 157.align 2 158PCCR0_A: .long 0xFFFE384E 159PDCR0_A: .long 0xFFFE386E 160PDCR1_A: .long 0xFFFE386C 161PDCR2_A: .long 0xFFFE386A 162PDCR3_A: .long 0xFFFE3868 163PBCR0_A: .long 0xFFFE382E 164PBCR1_A: .long 0xFFFE382C 165PBCR2_A: .long 0xFFFE382A 166PBCR3_A: .long 0xFFFE3828 167PBCR4_A: .long 0xFFFE3826 168PBCR5_A: .long 0xFFFE3824 169PCCR0_D: .word 0x1111 170PDCR0_D: .word 0x1111 171PDCR1_D: .word 0x1111 172PDCR2_D: .word 0x1111 173PDCR3_D: .word 0x1111 174PBCR0_D: .word 0x1110 175PBCR1_D: .word 0x1111 176PBCR2_D: .word 0x1111 177PBCR3_D: .word 0x1111 178PBCR4_D: .word 0x1111 179PBCR5_D: .word 0x0111 180.align 2 181CS0WCR_A: .long 0xFFFC0028 182CS0WCR_D: .long 0x00000B41 183CS0BCR_A: .long 0xFFFC0004 184CS0BCR_D: .long 0x10000400 185PJCR0_A: .long 0xFFFE390E 186PJCR0_D: .word 0x3300 187.align 2 188CS2WCR_A: .long 0xFFFC0030 189CS2WCR_D: .long 0x00000B01 190PCCR2_A: .long 0xFFFE384A 191PCCR2_D: .word 0x0001 192.align 2 193PCCR1_A: .long 0xFFFE384C 194PCCR1_D: .word 0x1111 195.align 2 196CS3BCR_A: .long 0xFFFC0010 197CS3BCR_D: .long 0x00004400 198CS3WCR_A: .long 0xFFFC0034 199CS3WCR_D: .long 0x0000288A 200SDCR_A: .long 0xFFFC004C 201SDCR_D: .long 0x00000812 202RTCOR_A: .long 0xFFFC0058 203RTCOR_D: .long 0xA55A0046 204RTCSR_A: .long 0xFFFC0050 205RTCSR_D: .long 0xA55A0010 206IBNR_A: .long 0xFFFE080E 207IBNR_D: .word 0x0000 208.align 2 209SDRAM_MODE: .long 0xFFFC5040 210REPEAT_D: .long 0x00000085 211