1/*
2 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 * Copyright (C) 2008 Nobuhiro Iwamatsu
5 *
6 * Based on board/renesas/rsk7203/lowlevel_init.S
7 *
8 * This file is released under the terms of GPL v2 and any later version.
9 * See the file COPYING in the root directory of the source tree for details.
10 */
11#include <config.h>
12#include <version.h>
13
14#include <asm/processor.h>
15#include <asm/macro.h>
16
17	.global	lowlevel_init
18
19	.text
20	.align	2
21
22lowlevel_init:
23	/* Cache setting */
24	write32	CCR1_A ,CCR1_D
25
26	/* io_set_cpg */
27	write8 STBCR3_A, STBCR3_D
28	write8 STBCR4_A, STBCR4_D
29	write8 STBCR5_A, STBCR5_D
30	write8 STBCR6_A, STBCR6_D
31	write8 STBCR7_A, STBCR7_D
32	write8 STBCR8_A, STBCR8_D
33
34	/* ConfigurePortPins */
35
36	/* Leaving LED1 ON for sanity test */
37	write16 PJCR1_A, PJCR1_D1
38	write16 PJCR2_A, PJCR2_D
39	write16 PJIOR0_A, PJIOR0_D1
40	write16 PJDR0_A, PJDR0_D
41	write16 PJPR0_A, PJPR0_D
42
43	/* Configure EN_PIN & RS_PIN */
44	write16 PGCR2_A, PGCR2_D
45	write16 PGIOR0_A, PGIOR0_D
46
47	/* Configure the port pins connected to UART */
48	write16 PJCR1_A, PJCR1_D2
49	write16 PJIOR0_A, PJIOR0_D2
50
51	/* Configure Operating Frequency */
52	write16	WTCSR_A, WTCSR_D0
53	write16	WTCSR_A, WTCSR_D1
54	write16	WTCNT_A, WTCNT_D
55
56	/* Control of RESBANK */
57	write16 IBNR_A, IBNR_D
58	/* Enable SCIF3 module */
59	write16 STBCR4_A, STBCR4_D
60
61	/* Set clock mode*/
62	write16	FRQCR_A, FRQCR_D
63
64	/* Configure Bus And Memory */
65init_bsc_cs0:
66
67pfc_settings:
68	write16 PCCR2_A, PCCR2_D
69	write16 PCCR1_A, PCCR1_D
70	write16 PCCR0_A, PCCR0_D
71
72	write16 PBCR0_A, PBCR0_D
73	write16 PBCR1_A, PBCR1_D
74	write16 PBCR2_A, PBCR2_D
75	write16 PBCR3_A, PBCR3_D
76	write16 PBCR4_A, PBCR4_D
77	write16 PBCR5_A, PBCR5_D
78
79	write16 PDCR0_A, PDCR0_D
80	write16 PDCR1_A, PDCR1_D
81	write16 PDCR2_A, PDCR2_D
82	write16 PDCR3_A, PDCR3_D
83
84	write32 CS0WCR_A, CS0WCR_D
85	write32 CS0BCR_A, CS0BCR_D
86
87init_bsc_cs2:
88	write16	PJCR0_A, PJCR0_D
89	write32	CS2WCR_A, CS2WCR_D
90
91init_sdram:
92	write32	CS3BCR_A, CS3BCR_D
93	write32	CS3WCR_A, CS3WCR_D
94	write32	SDCR_A, SDCR_D
95	write32	RTCOR_A, RTCOR_D
96	write32	RTCSR_A, RTCSR_D
97
98	/* wait 200us */
99	mov.l	REPEAT_D, r3
100	mov	#0, r2
101repeat0:
102	add	#1, r2
103	cmp/hs	r3, r2
104	bf	repeat0
105	nop
106
107	mov.l	SDRAM_MODE, r1
108	mov	#0, r0
109	mov.l	r0, @r1
110
111	nop
112	rts
113
114	.align 4
115
116CCR1_A:		.long CCR1
117CCR1_D:		.long 0x0000090B
118FRQCR_A:	.long 0xFFFE0010
119FRQCR_D:	.word 0x1003
120.align 2
121STBCR3_A:	.long 0xFFFE0408
122STBCR3_D:	.long 0x00000002
123STBCR4_A:	.long 0xFFFE040C
124STBCR4_D:	.word 0x0000
125.align 2
126STBCR5_A:	.long 0xFFFE0410
127STBCR5_D:	.long 0x00000010
128STBCR6_A:	.long 0xFFFE0414
129STBCR6_D:	.long 0x00000002
130STBCR7_A:	.long 0xFFFE0418
131STBCR7_D:	.long 0x0000002A
132STBCR8_A:	.long 0xFFFE041C
133STBCR8_D:	.long 0x0000007E
134PJCR1_A:	.long 0xFFFE390C
135PJCR1_D1:	.word 0x0000
136PJCR1_D2:	.word 0x0022
137PJCR2_A:	.long 0xFFFE390A
138PJCR2_D:	.word 0x0000
139.align 2
140PJIOR0_A:	.long 0xFFFE3912
141PJIOR0_D1:	.word 0x0FC0
142PJIOR0_D2:	.word 0x0FE0
143PJDR0_A:	.long 0xFFFE3916
144PJDR0_D:	.word 0x0FBF
145.align 2
146PJPR0_A:	.long 0xFFFE391A
147PJPR0_D:	.long 0x00000FBF
148PGCR2_A:	.long 0xFFFE38CA
149PGCR2_D:	.word 0x0000
150.align 2
151PGIOR0_A:	.long 0xFFFE38D2
152PGIOR0_D:	.word 0x03F0
153.align 2
154WTCSR_A:	.long 0xFFFE0000
155WTCSR_D0:	.word 0x0000
156WTCSR_D1:	.word 0x0000
157WTCNT_A:	.long 0xFFFE0002
158WTCNT_D:	.word 0x0000
159.align 2
160PCCR0_A:	.long 0xFFFE384E
161PDCR0_A:	.long 0xFFFE386E
162PDCR1_A:	.long 0xFFFE386C
163PDCR2_A:	.long 0xFFFE386A
164PDCR3_A:	.long 0xFFFE3868
165PBCR0_A:	.long 0xFFFE382E
166PBCR1_A:	.long 0xFFFE382C
167PBCR2_A:	.long 0xFFFE382A
168PBCR3_A:	.long 0xFFFE3828
169PBCR4_A:	.long 0xFFFE3826
170PBCR5_A:	.long 0xFFFE3824
171PCCR0_D:	.word 0x1111
172PDCR0_D:	.word 0x1111
173PDCR1_D:	.word 0x1111
174PDCR2_D:	.word 0x1111
175PDCR3_D:	.word 0x1111
176PBCR0_D:	.word 0x1110
177PBCR1_D:	.word 0x1111
178PBCR2_D:	.word 0x1111
179PBCR3_D:	.word 0x1111
180PBCR4_D:	.word 0x1111
181PBCR5_D:	.word 0x0111
182.align 2
183CS0WCR_A:	.long 0xFFFC0028
184CS0WCR_D:	.long 0x00000B41
185CS0BCR_A:	.long 0xFFFC0004
186CS0BCR_D:	.long 0x10000400
187PJCR0_A:	.long 0xFFFE390E
188PJCR0_D:	.word 0x3300
189.align 2
190CS2WCR_A:	.long 0xFFFC0030
191CS2WCR_D:	.long 0x00000B01
192PCCR2_A:	.long 0xFFFE384A
193PCCR2_D:	.word 0x0001
194.align 2
195PCCR1_A:	.long 0xFFFE384C
196PCCR1_D:	.word 0x1111
197.align 2
198CS3BCR_A:	.long 0xFFFC0010
199CS3BCR_D:	.long 0x00004400
200CS3WCR_A:	.long 0xFFFC0034
201CS3WCR_D:	.long 0x0000288A
202SDCR_A:		.long 0xFFFC004C
203SDCR_D:		.long 0x00000812
204RTCOR_A:	.long 0xFFFC0058
205RTCOR_D:	.long 0xA55A0046
206RTCSR_A:	.long 0xFFFC0050
207RTCSR_D:	.long 0xA55A0010
208IBNR_A:		.long 0xFFFE080E
209IBNR_D:	.word 0x0000
210.align 2
211SDRAM_MODE:	.long 0xFFFC5040
212REPEAT_D:	.long 0x00000085
213