1/*
2 * Copyright (C) 2008 Nobuhiro Iwamatsu
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 */
7#include <config.h>
8
9#include <asm/processor.h>
10#include <asm/macro.h>
11
12	.global	lowlevel_init
13
14	.text
15	.align	2
16
17lowlevel_init:
18	/* Cache setting */
19	write32	CCR1_A ,CCR1_D
20
21	/* ConfigurePortPins */
22	write16	PECRL3_A, PECRL3_D
23
24	write16	PCCRL4_A, PCCRL4_D0
25
26	write16	PECRL4_A, PECRL4_D0
27
28	write16	PEIORL_A, PEIORL_D0
29
30	write16	PCIORL_A, PCIORL_D
31
32	write16	PFCRH2_A, PFCRH2_D
33
34	write16	PFCRH3_A, PFCRH3_D
35
36	write16	PFCRH1_A, PFCRH1_D
37
38	write16	PFIORH_A, PFIORH_D
39
40	write16	PECRL1_A, PECRL1_D0
41
42	write16	PEIORL_A, PEIORL_D1
43
44	/* Configure Operating Frequency */
45	write16	WTCSR_A, WTCSR_D0
46
47	write16	WTCSR_A, WTCSR_D1
48
49	write16	WTCNT_A, WTCNT_D
50
51	/* Set clock mode*/
52	write16	FRQCR_A, FRQCR_D
53
54	/* Configure Bus And Memory */
55init_bsc_cs0:
56	write16	PCCRL4_A, PCCRL4_D1
57
58	write16	PECRL1_A, PECRL1_D1
59
60	write32	CMNCR_A, CMNCR_D
61
62	write32	CS0BCR_A, CS0BCR_D
63
64	write32	CS0WCR_A, CS0WCR_D
65
66init_bsc_cs1:
67	write16	PECRL4_A, PECRL4_D1
68
69	write32	CS1WCR_A, CS1WCR_D
70
71init_sdram:
72	write16	PCCRL2_A, PCCRL2_D
73
74	write16	PCCRL4_A, PCCRL4_D2
75
76	write16	PCCRL1_A, PCCRL1_D
77
78	write16	PCCRL3_A, PCCRL3_D
79
80	write32	CS3BCR_A, CS3BCR_D
81
82	write32	CS3WCR_A, CS3WCR_D
83
84	write32	SDCR_A, SDCR_D
85
86	write32	RTCOR_A, RTCOR_D
87
88	write32	RTCSR_A, RTCSR_D
89
90	/* wait 200us */
91	mov.l	REPEAT_D, r3
92	mov	#0, r2
93repeat0:
94	add	#1, r2
95	cmp/hs	r3, r2
96	bf	repeat0
97	nop
98
99	mov.l	SDRAM_MODE, r1
100	mov	#0, r0
101	mov.l	r0, @r1
102
103	nop
104	rts
105
106	.align 4
107
108CCR1_A:		.long CCR1
109CCR1_D:		.long 0x0000090B
110PCCRL4_A:	.long 0xFFFE3910
111PCCRL4_D0:	.word 0x0000
112.align 2
113PECRL4_A:	.long 0xFFFE3A10
114PECRL4_D0:	.word 0x0000
115.align 2
116PECRL3_A:	.long 0xFFFE3A12
117PECRL3_D:	.word 0x0000
118.align 2
119PEIORL_A:	.long 0xFFFE3A06
120PEIORL_D0:	.word 0x1C00
121PEIORL_D1:	.word 0x1C02
122PCIORL_A:	.long 0xFFFE3906
123PCIORL_D:	.word 0x4000
124.align 2
125PFCRH2_A:	.long 0xFFFE3A8C
126PFCRH2_D:	.word 0x0000
127.align 2
128PFCRH3_A:	.long 0xFFFE3A8A
129PFCRH3_D:	.word 0x0000
130.align 2
131PFCRH1_A:	.long 0xFFFE3A8E
132PFCRH1_D:	.word 0x0000
133.align 2
134PFIORH_A:	.long 0xFFFE3A84
135PFIORH_D:	.word 0x0729
136.align 2
137PECRL1_A:	.long 0xFFFE3A16
138PECRL1_D0:	.word 0x0033
139.align 2
140
141
142WTCSR_A:	.long 0xFFFE0000
143WTCSR_D0:	.word 0xA518
144WTCSR_D1:	.word 0xA51D
145WTCNT_A:	.long 0xFFFE0002
146WTCNT_D:	.word 0x5A84
147.align 2
148FRQCR_A:	.long 0xFFFE0010
149FRQCR_D:	.word 0x0104
150.align 2
151
152PCCRL4_D1:	.word 0x0010
153PECRL1_D1:	.word 0x0133
154
155CMNCR_A:	.long 0xFFFC0000
156CMNCR_D:	.long 0x00001810
157CS0BCR_A:	.long 0xFFFC0004
158CS0BCR_D:	.long 0x10000400
159CS0WCR_A:	.long 0xFFFC0028
160CS0WCR_D:	.long 0x00000B41
161PECRL4_D1:	.word 0x0100
162.align 2
163CS1WCR_A:	.long 0xFFFC002C
164CS1WCR_D:	.long 0x00000B01
165PCCRL4_D2:	.word 0x0011
166.align 2
167PCCRL3_A:	.long 0xFFFE3912
168PCCRL3_D:	.word 0x0011
169.align 2
170PCCRL2_A:	.long 0xFFFE3914
171PCCRL2_D:	.word 0x1111
172.align 2
173PCCRL1_A:	.long 0xFFFE3916
174PCCRL1_D:	.word 0x1010
175.align 2
176PDCRL4_A:	.long 0xFFFE3990
177PDCRL4_D:	.word 0x0011
178.align 2
179PDCRL3_A:	.long 0xFFFE3992
180PDCRL3_D:	.word 0x00011
181.align 2
182PDCRL2_A:	.long 0xFFFE3994
183PDCRL2_D:	.word 0x1111
184.align 2
185PDCRL1_A:	.long 0xFFFE3996
186PDCRL1_D:	.word 0x1000
187.align 2
188CS3BCR_A:	.long 0xFFFC0010
189CS3BCR_D:	.long 0x00004400
190CS3WCR_A:	.long 0xFFFC0034
191CS3WCR_D:	.long 0x00002892
192SDCR_A:		.long 0xFFFC004C
193SDCR_D:		.long 0x00000809
194RTCOR_A:	.long 0xFFFC0058
195RTCOR_D:	.long 0xA55A0041
196RTCSR_A:	.long 0xFFFC0050
197RTCSR_D:	.long 0xa55a0010
198
199SDRAM_MODE:	.long 0xFFFC5040
200REPEAT_D:	.long 0x00009C40
201