1/*
2 * Copyright (C) 2008 Nobuhiro Iwamatsu
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20#include <config.h>
21#include <version.h>
22
23#include <asm/processor.h>
24
25	.global	lowlevel_init
26
27	.text
28	.align	2
29
30lowlevel_init:
31	/* Cache setting */
32	mov.l CCR1_A ,r1
33	mov.l CCR1_D ,r0
34	mov.l r0,@r1
35
36	/* ConfigurePortPins */
37	mov.l PECRL3_A, r1
38	mov.l PECRL3_D, r0
39	mov.w r0,@r1
40
41	mov.l PCCRL4_A, r1
42	mov.l PCCRL4_D0, r0
43	mov.w r0,@r1
44
45	mov.l PECRL4_A, r1
46	mov.l PECRL4_D0, r0
47	mov.w r0,@r1
48
49	mov.l PEIORL_A, r1
50	mov.l PEIORL_D0, r0
51	mov.w r0,@r1
52
53	mov.l PCIORL_A, r1
54	mov.l PCIORL_D, r0
55	mov.w r0,@r1
56
57	mov.l PFCRH2_A, r1
58	mov.l PFCRH2_D, r0
59	mov.w r0,@r1
60
61	mov.l PFCRH3_A, r1
62	mov.l PFCRH3_D, r0
63	mov.w r0,@r1
64
65	mov.l PFCRH1_A, r1
66	mov.l PFCRH1_D, r0
67	mov.w r0,@r1
68
69	mov.l PFIORH_A, r1
70	mov.l PFIORH_D, r0
71	mov.w r0,@r1
72
73	mov.l PECRL1_A, r1
74	mov.l PECRL1_D0, r0
75	mov.w r0,@r1
76
77	mov.l PEIORL_A, r1
78	mov.l PEIORL_D1, r0
79	mov.w r0,@r1
80
81	/* Configure Operating Frequency */
82	mov.l WTCSR_A ,r1
83	mov.l WTCSR_D0 ,r0
84	mov.w r0,@r1
85
86	mov.l WTCSR_A ,r1
87	mov.l WTCSR_D1 ,r0
88	mov.w r0,@r1
89
90	mov.l WTCNT_A ,r1
91	mov.l WTCNT_D ,r0
92	mov.w r0,@r1
93
94	/* Set clock mode*/
95	mov.l FRQCR_A,r1
96	mov.l FRQCR_D,r0
97	mov.w r0,@r1
98
99	/* Configure Bus And Memory */
100init_bsc_cs0:
101	mov.l   PCCRL4_A,r1
102	mov.l   PCCRL4_D1,r0
103	mov.w   r0,@r1
104
105	mov.l   PECRL1_A,r1
106	mov.l   PECRL1_D1,r0
107	mov.w   r0,@r1
108
109	mov.l CMNCR_A,r1
110	mov.l CMNCR_D,r0
111	mov.l r0,@r1
112
113	mov.l SC0BCR_A,r1
114	mov.l SC0BCR_D,r0
115	mov.l r0,@r1
116
117	mov.l CS0WCR_A,r1
118	mov.l CS0WCR_D,r0
119	mov.l r0,@r1
120
121init_bsc_cs1:
122	mov.l   PECRL4_A,r1
123	mov.l   PECRL4_D1,r0
124	mov.w   r0,@r1
125
126	mov.l CS1WCR_A,r1
127	mov.l CS1WCR_D,r0
128	mov.l r0,@r1
129
130init_sdram:
131	mov.l	PCCRL2_A,r1
132	mov.l	PCCRL2_D,r0
133	mov.w	r0,@r1
134
135	mov.l	PCCRL4_A,r1
136	mov.l	PCCRL4_D2,r0
137	mov.w   r0,@r1
138
139	mov.l   PCCRL1_A,r1
140	mov.l	PCCRL1_D,r0
141	mov.w   r0,@r1
142
143	mov.l   PCCRL3_A,r1
144	mov.l	PCCRL3_D,r0
145	mov.w   r0,@r1
146
147	mov.l CS3BCR_A,r1
148	mov.l CS3BCR_D,r0
149	mov.l r0,@r1
150
151	mov.l CS3WCR_A,r1
152	mov.l CS3WCR_D,r0
153	mov.l r0,@r1
154
155	mov.l SDCR_A,r1
156	mov.l SDCR_D,r0
157	mov.l r0,@r1
158
159	mov.l RTCOR_A,r1
160	mov.l RTCOR_D,r0
161	mov.l r0,@r1
162
163	mov.l RTCSR_A,r1
164	mov.l RTCSR_D,r0
165	mov.l r0,@r1
166
167	/* wait 200us */
168	mov.l   REPEAT_D,r3
169	mov     #0,r2
170repeat0:
171	add     #1,r2
172	cmp/hs  r3,r2
173	bf      repeat0
174	nop
175
176	mov.l SDRAM_MODE, r1
177	mov   #0,r0
178	mov.l r0, @r1
179
180	nop
181	rts
182
183	.align 4
184
185CCR1_A:		.long CCR1
186CCR1_D:		.long 0x0000090B
187PCCRL4_A:	.long 0xFFFE3910
188PCCRL4_D0:	.long 0x00000000
189PECRL4_A:	.long 0xFFFE3A10
190PECRL4_D0:	.long 0x00000000
191PECRL3_A:	.long 0xFFFE3A12
192PECRL3_D:	.long 0x00000000
193PEIORL_A:	.long 0xFFFE3A06
194PEIORL_D0:	.long 0x00001C00
195PEIORL_D1:	.long 0x00001C02
196PCIORL_A:	.long 0xFFFE3906
197PCIORL_D:	.long 0x00004000
198PFCRH2_A:	.long 0xFFFE3A8C
199PFCRH2_D:	.long 0x00000000
200PFCRH3_A:	.long 0xFFFE3A8A
201PFCRH3_D:	.long 0x00000000
202PFCRH1_A:	.long 0xFFFE3A8E
203PFCRH1_D:	.long 0x00000000
204PFIORH_A:	.long 0xFFFE3A84
205PFIORH_D:	.long 0x00000729
206PECRL1_A:	.long 0xFFFE3A16
207PECRL1_D0:	.long 0x00000033
208
209
210WTCSR_A:	.long 0xFFFE0000
211WTCSR_D0: 	.long 0x0000A518
212WTCSR_D1: 	.long 0x0000A51D
213WTCNT_A:	.long 0xFFFE0002
214WTCNT_D:	.long 0x00005A84
215FRQCR_A:	.long 0xFFFE0010
216FRQCR_D:	.long 0x00000104
217
218PCCRL4_D1:	.long 0x00000010
219PECRL1_D1:	.long 0x00000133
220
221CMNCR_A:	.long 0xFFFC0000
222CMNCR_D:	.long 0x00001810
223SC0BCR_A:	.long 0xFFFC0004
224SC0BCR_D:	.long 0x10000400
225CS0WCR_A:	.long 0xFFFC0028
226CS0WCR_D:	.long 0x00000B41
227PECRL4_D1:	.long 0x00000100
228CS1WCR_A:	.long 0xFFFC002C
229CS1WCR_D:	.long 0x00000B01
230PCCRL4_D2:	.long 0x00000011
231PCCRL3_A:	.long 0xFFFE3912
232PCCRL3_D:	.long 0x00000011
233PCCRL2_A:	.long 0xFFFE3914
234PCCRL2_D:	.long 0x00001111
235PCCRL1_A:	.long 0xFFFE3916
236PCCRL1_D:	.long 0x00001010
237PDCRL4_A:	.long 0xFFFE3990
238PDCRL4_D:	.long 0x00000011
239PDCRL3_A:	.long 0xFFFE3992
240PDCRL3_D:	.long 0x00000011
241PDCRL2_A:	.long 0xFFFE3994
242PDCRL2_D:	.long 0x00001111
243PDCRL1_A:	.long 0xFFFE3996
244PDCRL1_D:	.long 0x00001000
245CS3BCR_A:	.long 0xFFFC0010
246CS3BCR_D:	.long 0x00004400
247CS3WCR_A:	.long 0xFFFC0034
248CS3WCR_D:	.long 0x00002892
249SDCR_A:		.long 0xFFFC004C
250SDCR_D:		.long 0x00000809
251RTCOR_A:	.long 0xFFFC0058
252RTCOR_D:	.long 0xA55A0041
253RTCSR_A:	.long 0xFFFC0050
254RTCSR_D:	.long 0xa55a0010
255
256STBCR3_A:	.long 0xFFFE0408
257STBCR3_D:	.long 0x00000000
258STBCR4_A:	.long 0xFFFE040C
259STBCR4_D:	.long 0x00000008
260STBCR5_A:	.long 0xFFFE0410
261STBCR5_D:	.long 0x00000000
262STBCR6_A: 	.long 0xFFFE0414
263STBCR6_D:	.long 0x00000002
264SDRAM_MODE:	.long 0xFFFC5040
265REPEAT_D:	.long 0x00009C40
266