1/*
2 * Copyright (C) 2008 Nobuhiro Iwamatsu
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20#include <config.h>
21#include <version.h>
22
23#include <asm/processor.h>
24#include <asm/macro.h>
25
26	.global	lowlevel_init
27
28	.text
29	.align	2
30
31lowlevel_init:
32	/* Cache setting */
33	write32	CCR1_A ,CCR1_D
34
35	/* ConfigurePortPins */
36	write16	PECRL3_A, PECRL3_D
37
38	write16	PCCRL4_A, PCCRL4_D0
39
40	write16	PECRL4_A, PECRL4_D0
41
42	write16	PEIORL_A, PEIORL_D0
43
44	write16	PCIORL_A, PCIORL_D
45
46	write16	PFCRH2_A, PFCRH2_D
47
48	write16	PFCRH3_A, PFCRH3_D
49
50	write16	PFCRH1_A, PFCRH1_D
51
52	write16	PFIORH_A, PFIORH_D
53
54	write16	PECRL1_A, PECRL1_D0
55
56	write16	PEIORL_A, PEIORL_D1
57
58	/* Configure Operating Frequency */
59	write16	WTCSR_A, WTCSR_D0
60
61	write16	WTCSR_A, WTCSR_D1
62
63	write16	WTCNT_A, WTCNT_D
64
65	/* Set clock mode*/
66	write16	FRQCR_A, FRQCR_D
67
68	/* Configure Bus And Memory */
69init_bsc_cs0:
70	write16	PCCRL4_A, PCCRL4_D1
71
72	write16	PECRL1_A, PECRL1_D1
73
74	write32	CMNCR_A, CMNCR_D
75
76	write32	CS0BCR_A, CS0BCR_D
77
78	write32	CS0WCR_A, CS0WCR_D
79
80init_bsc_cs1:
81	write16	PECRL4_A, PECRL4_D1
82
83	write32	CS1WCR_A, CS1WCR_D
84
85init_sdram:
86	write16	PCCRL2_A, PCCRL2_D
87
88	write16	PCCRL4_A, PCCRL4_D2
89
90	write16	PCCRL1_A, PCCRL1_D
91
92	write16	PCCRL3_A, PCCRL3_D
93
94	write32	CS3BCR_A, CS3BCR_D
95
96	write32	CS3WCR_A, CS3WCR_D
97
98	write32	SDCR_A, SDCR_D
99
100	write32	RTCOR_A, RTCOR_D
101
102	write32	RTCSR_A, RTCSR_D
103
104	/* wait 200us */
105	mov.l	REPEAT_D, r3
106	mov	#0, r2
107repeat0:
108	add	#1, r2
109	cmp/hs	r3, r2
110	bf	repeat0
111	nop
112
113	mov.l	SDRAM_MODE, r1
114	mov	#0, r0
115	mov.l	r0, @r1
116
117	nop
118	rts
119
120	.align 4
121
122CCR1_A:		.long CCR1
123CCR1_D:		.long 0x0000090B
124PCCRL4_A:	.long 0xFFFE3910
125PCCRL4_D0:	.word 0x0000
126.align 2
127PECRL4_A:	.long 0xFFFE3A10
128PECRL4_D0:	.word 0x0000
129.align 2
130PECRL3_A:	.long 0xFFFE3A12
131PECRL3_D:	.word 0x0000
132.align 2
133PEIORL_A:	.long 0xFFFE3A06
134PEIORL_D0:	.word 0x1C00
135PEIORL_D1:	.word 0x1C02
136PCIORL_A:	.long 0xFFFE3906
137PCIORL_D:	.word 0x4000
138.align 2
139PFCRH2_A:	.long 0xFFFE3A8C
140PFCRH2_D:	.word 0x0000
141.align 2
142PFCRH3_A:	.long 0xFFFE3A8A
143PFCRH3_D:	.word 0x0000
144.align 2
145PFCRH1_A:	.long 0xFFFE3A8E
146PFCRH1_D:	.word 0x0000
147.align 2
148PFIORH_A:	.long 0xFFFE3A84
149PFIORH_D:	.word 0x0729
150.align 2
151PECRL1_A:	.long 0xFFFE3A16
152PECRL1_D0:	.word 0x0033
153.align 2
154
155
156WTCSR_A:	.long 0xFFFE0000
157WTCSR_D0:	.word 0xA518
158WTCSR_D1:	.word 0xA51D
159WTCNT_A:	.long 0xFFFE0002
160WTCNT_D:	.word 0x5A84
161.align 2
162FRQCR_A:	.long 0xFFFE0010
163FRQCR_D:	.word 0x0104
164.align 2
165
166PCCRL4_D1:	.word 0x0010
167PECRL1_D1:	.word 0x0133
168
169CMNCR_A:	.long 0xFFFC0000
170CMNCR_D:	.long 0x00001810
171CS0BCR_A:	.long 0xFFFC0004
172CS0BCR_D:	.long 0x10000400
173CS0WCR_A:	.long 0xFFFC0028
174CS0WCR_D:	.long 0x00000B41
175PECRL4_D1:	.word 0x0100
176.align 2
177CS1WCR_A:	.long 0xFFFC002C
178CS1WCR_D:	.long 0x00000B01
179PCCRL4_D2:	.word 0x0011
180.align 2
181PCCRL3_A:	.long 0xFFFE3912
182PCCRL3_D:	.word 0x0011
183.align 2
184PCCRL2_A:	.long 0xFFFE3914
185PCCRL2_D:	.word 0x1111
186.align 2
187PCCRL1_A:	.long 0xFFFE3916
188PCCRL1_D:	.word 0x1010
189.align 2
190PDCRL4_A:	.long 0xFFFE3990
191PDCRL4_D:	.word 0x0011
192.align 2
193PDCRL3_A:	.long 0xFFFE3992
194PDCRL3_D:	.word 0x00011
195.align 2
196PDCRL2_A:	.long 0xFFFE3994
197PDCRL2_D:	.word 0x1111
198.align 2
199PDCRL1_A:	.long 0xFFFE3996
200PDCRL1_D:	.word 0x1000
201.align 2
202CS3BCR_A:	.long 0xFFFC0010
203CS3BCR_D:	.long 0x00004400
204CS3WCR_A:	.long 0xFFFC0034
205CS3WCR_D:	.long 0x00002892
206SDCR_A:		.long 0xFFFC004C
207SDCR_D:		.long 0x00000809
208RTCOR_A:	.long 0xFFFC0058
209RTCOR_D:	.long 0xA55A0041
210RTCSR_A:	.long 0xFFFC0050
211RTCSR_D:	.long 0xa55a0010
212
213SDRAM_MODE:	.long 0xFFFC5040
214REPEAT_D:	.long 0x00009C40
215