1 /* 2 * Copyright (C) 2007 Nobuhiro Iwamatsu 3 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 4 * 5 * u-boot/board/r7780mp/r7780mp.h 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef _BOARD_R7780MP_R7780MP_H_ 24 #define _BOARD_R7780MP_R7780MP_H_ 25 26 /* R7780MP's FPGA register map */ 27 #define FPGA_BASE 0xa4000000 28 #define FPGA_IRLMSK (FPGA_BASE + 0x00) 29 #define FPGA_IRLMON (FPGA_BASE + 0x02) 30 #define FPGA_IRLPRI1 (FPGA_BASE + 0x04) 31 #define FPGA_IRLPRI2 (FPGA_BASE + 0x06) 32 #define FPGA_IRLPRI3 (FPGA_BASE + 0x08) 33 #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) 34 #define FPGA_RSTCTL (FPGA_BASE + 0x0C) 35 #define FPGA_PCIBD (FPGA_BASE + 0x0E) 36 #define FPGA_PCICD (FPGA_BASE + 0x10) 37 #define FPGA_EXTGIO (FPGA_BASE + 0x16) 38 #define FPGA_IVDRMON (FPGA_BASE + 0x18) 39 #define FPGA_IVDRCR (FPGA_BASE + 0x1A) 40 #define FPGA_OBLED (FPGA_BASE + 0x1C) 41 #define FPGA_OBSW (FPGA_BASE + 0x1E) 42 #define FPGA_TPCTL (FPGA_BASE + 0x100) 43 #define FPGA_TPDCKCTL (FPGA_BASE + 0x102) 44 #define FPGA_TPCLR (FPGA_BASE + 0x104) 45 #define FPGA_TPXPOS (FPGA_BASE + 0x106) 46 #define FPGA_TPYPOS (FPGA_BASE + 0x108) 47 #define FPGA_DBSW (FPGA_BASE + 0x200) 48 #define FPGA_VERSION (FPGA_BASE + 0x700) 49 #define FPGA_CFCTL (FPGA_BASE + 0x300) 50 #define FPGA_CFPOW (FPGA_BASE + 0x302) 51 #define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) 52 #define FPGA_PMR (FPGA_BASE + 0x900) 53 54 #endif /* _BOARD_R7780RP_R7780RP_H_ */ 55