1/*
2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
3 *
4 * u-boot/board/r7780mp/lowlevel_init.S
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <config.h>
10#include <asm/processor.h>
11#include <asm/macro.h>
12
13/*
14 * Board specific low level init code, called _very_ early in the
15 * startup sequence. Relocation to SDRAM has not happened yet, no
16 * stack is available, bss section has not been initialised, etc.
17 *
18 * (Note: As no stack is available, no subroutines can be called...).
19 */
20
21	.global	lowlevel_init
22
23	.text
24	.align	2
25
26lowlevel_init:
27
28	write32	CCR_A, CCR_D		/* Address of Cache Control Register */
29					/* Instruction Cache Invalidate */
30
31	write32	FRQCR_A, FRQCR_D	/* Frequency control register */
32
33	/* pin_multi_setting */
34	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR1
35
36	write32	BBG_PMSR1_A, BBG_PMSR1_D
37
38	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR2
39
40	write32	BBG_PMSR2_A, BBG_PMSR2_D
41
42	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR3
43
44	write32	BBG_PMSR3_A, BBG_PMSR3_D
45
46	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR4
47
48	write32	BBG_PMSR4_A, BBG_PMSR4_D
49
50	write32	BBG_PMMR_A, BBG_PMMR_D_PMSRG
51
52	write32	BBG_PMSRG_A, BBG_PMSRG_D
53
54	/* cpg_setting */
55	write32	FRQCR_A, FRQCR_D
56
57	write32	DLLCSR_A, DLLCSR_D
58
59	nop
60	nop
61	nop
62	nop
63	nop
64	nop
65	nop
66	nop
67	nop
68	nop
69
70	/* wait 200us */
71	mov.l	REPEAT0_R3, r3
72	mov	#0, r2
73repeat0:
74	add	#1, r2
75	cmp/hs	r3, r2
76	bf	repeat0
77	nop
78
79	/* bsc_setting */
80	write32	MMSELR_A, MMSELR_D
81
82	write32	BCR_A, BCR_D
83
84	write32	CS0BCR_A, CS0BCR_D
85
86	write32	CS1BCR_A, CS1BCR_D
87
88	write32	CS2BCR_A, CS2BCR_D
89
90	write32	CS4BCR_A, CS4BCR_D
91
92	write32	CS5BCR_A, CS5BCR_D
93
94	write32	CS6BCR_A, CS6BCR_D
95
96	write32	CS0WCR_A, CS0WCR_D
97
98	write32	CS1WCR_A, CS1WCR_D
99
100	write32	CS2WCR_A, CS2WCR_D
101
102	write32	CS4WCR_A, CS4WCR_D
103
104	write32	CS5WCR_A, CS5WCR_D
105
106	write32	CS6WCR_A, CS6WCR_D
107
108	write32	CS5PCR_A, CS5PCR_D
109
110	write32	CS6PCR_A, CS6PCR_D
111
112	/* ddr_setting */
113	/* wait 200us */
114	mov.l	REPEAT0_R3, r3
115	mov	#0, r2
116repeat1:
117	add	#1, r2
118	cmp/hs	r3, r2
119	bf	repeat1
120	nop
121
122	mov.l	MIM_U_A, r0
123	mov.l	MIM_U_D, r1
124	synco
125	mov.l	r1, @r0
126	synco
127
128	mov.l	MIM_L_A, r0
129	mov.l	MIM_L_D0, r1
130	synco
131	mov.l	r1, @r0
132	synco
133
134	mov.l	STR_L_A, r0
135	mov.l	STR_L_D, r1
136	synco
137	mov.l	r1, @r0
138	synco
139
140	mov.l	SDR_L_A, r0
141	mov.l	SDR_L_D, r1
142	synco
143	mov.l	r1, @r0
144	synco
145
146	nop
147	nop
148	nop
149	nop
150
151	mov.l	SCR_L_A, r0
152	mov.l	SCR_L_D0, r1
153	synco
154	mov.l	r1, @r0
155	synco
156
157	mov.l	SCR_L_A, r0
158	mov.l	SCR_L_D1, r1
159	synco
160	mov.l	r1, @r0
161	synco
162
163	nop
164	nop
165	nop
166
167	mov.l	EMRS_A, r0
168	mov.l	EMRS_D, r1
169	synco
170	mov.l	r1, @r0
171	synco
172
173	nop
174	nop
175	nop
176
177	mov.l	MRS1_A, r0
178	mov.l	MRS1_D, r1
179	synco
180	mov.l	r1, @r0
181	synco
182
183	nop
184	nop
185	nop
186
187	mov.l	SCR_L_A, r0
188	mov.l	SCR_L_D2, r1
189	synco
190	mov.l	r1, @r0
191	synco
192
193	nop
194	nop
195	nop
196
197	mov.l	SCR_L_A, r0
198	mov.l	SCR_L_D3, r1
199	synco
200	mov.l	r1, @r0
201	synco
202
203	nop
204	nop
205	nop
206
207	mov.l	SCR_L_A, r0
208	mov.l	SCR_L_D4, r1
209	synco
210	mov.l	r1, @r0
211	synco
212
213	nop
214	nop
215	nop
216
217	mov.l	MRS2_A, r0
218	mov.l	MRS2_D, r1
219	synco
220	mov.l	r1, @r0
221	synco
222
223	nop
224	nop
225	nop
226
227	mov.l	SCR_L_A, r0
228	mov.l	SCR_L_D5, r1
229	synco
230	mov.l	r1, @r0
231	synco
232
233	/* wait 200us */
234	mov.l	REPEAT0_R1, r3
235	mov	#0, r2
236repeat2:
237	add	#1, r2
238	cmp/hs	r3, r2
239	bf	repeat2
240
241	synco
242
243	mov.l	MIM_L_A, r0
244	mov.l	MIM_L_D1, r1
245	synco
246	mov.l	r1, @r0
247	synco
248
249	rts
250	nop
251	.align	4
252
253RWTCSR_D_1:		.word	0xA507
254RWTCSR_D_2:		.word	0xA507
255RWTCNT_D:		.word	0x5A00
256	.align	2
257
258BBG_PMMR_A:		.long	0xFF800010
259BBG_PMSR1_A:		.long	0xFF800014
260BBG_PMSR2_A:		.long	0xFF800018
261BBG_PMSR3_A:		.long	0xFF80001C
262BBG_PMSR4_A:		.long	0xFF800020
263BBG_PMSRG_A:		.long	0xFF800024
264
265BBG_PMMR_D_PMSR1:	.long	0xffffbffd
266BBG_PMSR1_D:		.long	0x00004002
267BBG_PMMR_D_PMSR2:	.long	0xfc21a7ff
268BBG_PMSR2_D:		.long	0x03de5800
269BBG_PMMR_D_PMSR3:	.long	0xfffffff8
270BBG_PMSR3_D:		.long	0x00000007
271BBG_PMMR_D_PMSR4:	.long	0xdffdfff9
272BBG_PMSR4_D:		.long	0x20020006
273BBG_PMMR_D_PMSRG:	.long	0xffffffff
274BBG_PMSRG_D:		.long	0x00000000
275
276FRQCR_A:		.long	FRQCR
277DLLCSR_A:		.long	0xffc40010
278FRQCR_D:		.long	0x40233035
279DLLCSR_D:		.long	0x00000000
280
281/* for DDR-SDRAM */
282MIM_U_A:		.long	MIM_1
283MIM_L_A:		.long	MIM_2
284SCR_U_A:		.long	SCR_1
285SCR_L_A:		.long	SCR_2
286STR_U_A:		.long	STR_1
287STR_L_A:		.long	STR_2
288SDR_U_A:		.long	SDR_1
289SDR_L_A:		.long	SDR_2
290
291EMRS_A:			.long	0xFEC02000
292MRS1_A:			.long	0xFEC00B08
293MRS2_A:			.long	0xFEC00308
294
295MIM_U_D:		.long	0x00004000
296MIM_L_D0:		.long	0x03e80009
297MIM_L_D1:		.long	0x03e80209
298SCR_L_D0:		.long	0x3
299SCR_L_D1:		.long	0x2
300SCR_L_D2:		.long	0x2
301SCR_L_D3:		.long	0x4
302SCR_L_D4:		.long	0x4
303SCR_L_D5:		.long	0x0
304STR_L_D:		.long	0x000f0000
305SDR_L_D:		.long	0x00000400
306EMRS_D:			.long	0x0
307MRS1_D:			.long	0x0
308MRS2_D:			.long	0x0
309
310/* Cache Controller */
311CCR_A:			.long	CCR
312MMUCR_A:		.long	MMUCR
313RWTCNT_A:		.long	WTCNT
314
315CCR_D:			.long	0x0000090b
316CCR_D_2:		.long	0x00000103
317MMUCR_D:		.long	0x00000004
318MSTPCR0_D:		.long	0x00001001
319MSTPCR2_D:		.long	0xffffffff
320
321/* local Bus State Controller */
322MMSELR_A:		.long	MMSELR
323BCR_A:			.long	BCR
324CS0BCR_A:		.long	CS0BCR
325CS1BCR_A:		.long	CS1BCR
326CS2BCR_A:		.long	CS2BCR
327CS4BCR_A:		.long	CS4BCR
328CS5BCR_A:		.long	CS5BCR
329CS6BCR_A:		.long	CS6BCR
330CS0WCR_A:		.long	CS0WCR
331CS1WCR_A:		.long	CS1WCR
332CS2WCR_A:		.long	CS2WCR
333CS4WCR_A:		.long	CS4WCR
334CS5WCR_A:		.long	CS5WCR
335CS6WCR_A:		.long	CS6WCR
336CS5PCR_A:		.long	CS5PCR
337CS6PCR_A:		.long	CS6PCR
338
339MMSELR_D:		.long	0xA5A50003
340BCR_D:			.long	0x00000000
341CS0BCR_D:		.long	0x77777770
342CS1BCR_D:		.long	0x77777670
343CS2BCR_D:		.long	0x77777770
344CS4BCR_D:		.long	0x77777770
345CS5BCR_D:		.long	0x77777670
346CS6BCR_D:		.long	0x77777770
347CS0WCR_D:		.long	0x00020006
348CS1WCR_D:		.long	0x00232304
349CS2WCR_D:		.long	0x7777770F
350CS4WCR_D:		.long	0x7777770F
351CS5WCR_D:		.long	0x00101006
352CS6WCR_D:		.long	0x77777703
353CS5PCR_D:		.long	0x77000000
354CS6PCR_D:		.long	0x77000000
355
356REPEAT0_R3:		.long	0x00002000
357REPEAT0_R1:		.long	0x0000200
358