1/*
2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
3 *
4 * u-boot/board/r7780mp/lowlevel_init.S
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <config.h>
10#include <version.h>
11#include <asm/processor.h>
12#include <asm/macro.h>
13
14/*
15 * Board specific low level init code, called _very_ early in the
16 * startup sequence. Relocation to SDRAM has not happened yet, no
17 * stack is available, bss section has not been initialised, etc.
18 *
19 * (Note: As no stack is available, no subroutines can be called...).
20 */
21
22	.global	lowlevel_init
23
24	.text
25	.align	2
26
27lowlevel_init:
28
29	write32	CCR_A, CCR_D		/* Address of Cache Control Register */
30					/* Instruction Cache Invalidate */
31
32	write32	FRQCR_A, FRQCR_D	/* Frequency control register */
33
34	/* pin_multi_setting */
35	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR1
36
37	write32	BBG_PMSR1_A, BBG_PMSR1_D
38
39	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR2
40
41	write32	BBG_PMSR2_A, BBG_PMSR2_D
42
43	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR3
44
45	write32	BBG_PMSR3_A, BBG_PMSR3_D
46
47	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR4
48
49	write32	BBG_PMSR4_A, BBG_PMSR4_D
50
51	write32	BBG_PMMR_A, BBG_PMMR_D_PMSRG
52
53	write32	BBG_PMSRG_A, BBG_PMSRG_D
54
55	/* cpg_setting */
56	write32	FRQCR_A, FRQCR_D
57
58	write32	DLLCSR_A, DLLCSR_D
59
60	nop
61	nop
62	nop
63	nop
64	nop
65	nop
66	nop
67	nop
68	nop
69	nop
70
71	/* wait 200us */
72	mov.l	REPEAT0_R3, r3
73	mov	#0, r2
74repeat0:
75	add	#1, r2
76	cmp/hs	r3, r2
77	bf	repeat0
78	nop
79
80	/* bsc_setting */
81	write32	MMSELR_A, MMSELR_D
82
83	write32	BCR_A, BCR_D
84
85	write32	CS0BCR_A, CS0BCR_D
86
87	write32	CS1BCR_A, CS1BCR_D
88
89	write32	CS2BCR_A, CS2BCR_D
90
91	write32	CS4BCR_A, CS4BCR_D
92
93	write32	CS5BCR_A, CS5BCR_D
94
95	write32	CS6BCR_A, CS6BCR_D
96
97	write32	CS0WCR_A, CS0WCR_D
98
99	write32	CS1WCR_A, CS1WCR_D
100
101	write32	CS2WCR_A, CS2WCR_D
102
103	write32	CS4WCR_A, CS4WCR_D
104
105	write32	CS5WCR_A, CS5WCR_D
106
107	write32	CS6WCR_A, CS6WCR_D
108
109	write32	CS5PCR_A, CS5PCR_D
110
111	write32	CS6PCR_A, CS6PCR_D
112
113	/* ddr_setting */
114	/* wait 200us */
115	mov.l	REPEAT0_R3, r3
116	mov	#0, r2
117repeat1:
118	add	#1, r2
119	cmp/hs	r3, r2
120	bf	repeat1
121	nop
122
123	mov.l	MIM_U_A, r0
124	mov.l	MIM_U_D, r1
125	synco
126	mov.l	r1, @r0
127	synco
128
129	mov.l	MIM_L_A, r0
130	mov.l	MIM_L_D0, r1
131	synco
132	mov.l	r1, @r0
133	synco
134
135	mov.l	STR_L_A, r0
136	mov.l	STR_L_D, r1
137	synco
138	mov.l	r1, @r0
139	synco
140
141	mov.l	SDR_L_A, r0
142	mov.l	SDR_L_D, r1
143	synco
144	mov.l	r1, @r0
145	synco
146
147	nop
148	nop
149	nop
150	nop
151
152	mov.l	SCR_L_A, r0
153	mov.l	SCR_L_D0, r1
154	synco
155	mov.l	r1, @r0
156	synco
157
158	mov.l	SCR_L_A, r0
159	mov.l	SCR_L_D1, r1
160	synco
161	mov.l	r1, @r0
162	synco
163
164	nop
165	nop
166	nop
167
168	mov.l	EMRS_A, r0
169	mov.l	EMRS_D, r1
170	synco
171	mov.l	r1, @r0
172	synco
173
174	nop
175	nop
176	nop
177
178	mov.l	MRS1_A, r0
179	mov.l	MRS1_D, r1
180	synco
181	mov.l	r1, @r0
182	synco
183
184	nop
185	nop
186	nop
187
188	mov.l	SCR_L_A, r0
189	mov.l	SCR_L_D2, r1
190	synco
191	mov.l	r1, @r0
192	synco
193
194	nop
195	nop
196	nop
197
198	mov.l	SCR_L_A, r0
199	mov.l	SCR_L_D3, r1
200	synco
201	mov.l	r1, @r0
202	synco
203
204	nop
205	nop
206	nop
207
208	mov.l	SCR_L_A, r0
209	mov.l	SCR_L_D4, r1
210	synco
211	mov.l	r1, @r0
212	synco
213
214	nop
215	nop
216	nop
217
218	mov.l	MRS2_A, r0
219	mov.l	MRS2_D, r1
220	synco
221	mov.l	r1, @r0
222	synco
223
224	nop
225	nop
226	nop
227
228	mov.l	SCR_L_A, r0
229	mov.l	SCR_L_D5, r1
230	synco
231	mov.l	r1, @r0
232	synco
233
234	/* wait 200us */
235	mov.l	REPEAT0_R1, r3
236	mov	#0, r2
237repeat2:
238	add	#1, r2
239	cmp/hs	r3, r2
240	bf	repeat2
241
242	synco
243
244	mov.l	MIM_L_A, r0
245	mov.l	MIM_L_D1, r1
246	synco
247	mov.l	r1, @r0
248	synco
249
250	rts
251	nop
252	.align	4
253
254RWTCSR_D_1:		.word	0xA507
255RWTCSR_D_2:		.word	0xA507
256RWTCNT_D:		.word	0x5A00
257	.align	2
258
259BBG_PMMR_A:		.long	0xFF800010
260BBG_PMSR1_A:		.long	0xFF800014
261BBG_PMSR2_A:		.long	0xFF800018
262BBG_PMSR3_A:		.long	0xFF80001C
263BBG_PMSR4_A:		.long	0xFF800020
264BBG_PMSRG_A:		.long	0xFF800024
265
266BBG_PMMR_D_PMSR1:	.long	0xffffbffd
267BBG_PMSR1_D:		.long	0x00004002
268BBG_PMMR_D_PMSR2:	.long	0xfc21a7ff
269BBG_PMSR2_D:		.long	0x03de5800
270BBG_PMMR_D_PMSR3:	.long	0xfffffff8
271BBG_PMSR3_D:		.long	0x00000007
272BBG_PMMR_D_PMSR4:	.long	0xdffdfff9
273BBG_PMSR4_D:		.long	0x20020006
274BBG_PMMR_D_PMSRG:	.long	0xffffffff
275BBG_PMSRG_D:		.long	0x00000000
276
277FRQCR_A:		.long	FRQCR
278DLLCSR_A:		.long	0xffc40010
279FRQCR_D:		.long	0x40233035
280DLLCSR_D:		.long	0x00000000
281
282/* for DDR-SDRAM */
283MIM_U_A:		.long	MIM_1
284MIM_L_A:		.long	MIM_2
285SCR_U_A:		.long	SCR_1
286SCR_L_A:		.long	SCR_2
287STR_U_A:		.long	STR_1
288STR_L_A:		.long	STR_2
289SDR_U_A:		.long	SDR_1
290SDR_L_A:		.long	SDR_2
291
292EMRS_A:			.long	0xFEC02000
293MRS1_A:			.long	0xFEC00B08
294MRS2_A:			.long	0xFEC00308
295
296MIM_U_D:		.long	0x00004000
297MIM_L_D0:		.long	0x03e80009
298MIM_L_D1:		.long	0x03e80209
299SCR_L_D0:		.long	0x3
300SCR_L_D1:		.long	0x2
301SCR_L_D2:		.long	0x2
302SCR_L_D3:		.long	0x4
303SCR_L_D4:		.long	0x4
304SCR_L_D5:		.long	0x0
305STR_L_D:		.long	0x000f0000
306SDR_L_D:		.long	0x00000400
307EMRS_D:			.long	0x0
308MRS1_D:			.long	0x0
309MRS2_D:			.long	0x0
310
311/* Cache Controller */
312CCR_A:			.long	CCR
313MMUCR_A:		.long	MMUCR
314RWTCNT_A:		.long	WTCNT
315
316CCR_D:			.long	0x0000090b
317CCR_D_2:		.long	0x00000103
318MMUCR_D:		.long	0x00000004
319MSTPCR0_D:		.long	0x00001001
320MSTPCR2_D:		.long	0xffffffff
321
322/* local Bus State Controller */
323MMSELR_A:		.long	MMSELR
324BCR_A:			.long	BCR
325CS0BCR_A:		.long	CS0BCR
326CS1BCR_A:		.long	CS1BCR
327CS2BCR_A:		.long	CS2BCR
328CS4BCR_A:		.long	CS4BCR
329CS5BCR_A:		.long	CS5BCR
330CS6BCR_A:		.long	CS6BCR
331CS0WCR_A:		.long	CS0WCR
332CS1WCR_A:		.long	CS1WCR
333CS2WCR_A:		.long	CS2WCR
334CS4WCR_A:		.long	CS4WCR
335CS5WCR_A:		.long	CS5WCR
336CS6WCR_A:		.long	CS6WCR
337CS5PCR_A:		.long	CS5PCR
338CS6PCR_A:		.long	CS6PCR
339
340MMSELR_D:		.long	0xA5A50003
341BCR_D:			.long	0x00000000
342CS0BCR_D:		.long	0x77777770
343CS1BCR_D:		.long	0x77777670
344CS2BCR_D:		.long	0x77777770
345CS4BCR_D:		.long	0x77777770
346CS5BCR_D:		.long	0x77777670
347CS6BCR_D:		.long	0x77777770
348CS0WCR_D:		.long	0x00020006
349CS1WCR_D:		.long	0x00232304
350CS2WCR_D:		.long	0x7777770F
351CS4WCR_D:		.long	0x7777770F
352CS5WCR_D:		.long	0x00101006
353CS6WCR_D:		.long	0x77777703
354CS5PCR_D:		.long	0x77000000
355CS6PCR_D:		.long	0x77000000
356
357REPEAT0_R3:		.long	0x00002000
358REPEAT0_R1:		.long	0x0000200
359