1/*
2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
3 *
4 * u-boot/board/r7780mp/lowlevel_init.S
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <config.h>
23#include <version.h>
24#include <asm/processor.h>
25#include <asm/macro.h>
26
27/*
28 * Board specific low level init code, called _very_ early in the
29 * startup sequence. Relocation to SDRAM has not happened yet, no
30 * stack is available, bss section has not been initialised, etc.
31 *
32 * (Note: As no stack is available, no subroutines can be called...).
33 */
34
35	.global	lowlevel_init
36
37	.text
38	.align	2
39
40lowlevel_init:
41
42	write32	CCR_A, CCR_D		/* Address of Cache Control Register */
43					/* Instruction Cache Invalidate */
44
45	write32	FRQCR_A, FRQCR_D	/* Frequency control register */
46
47	/* pin_multi_setting */
48	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR1
49
50	write32	BBG_PMSR1_A, BBG_PMSR1_D
51
52	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR2
53
54	write32	BBG_PMSR2_A, BBG_PMSR2_D
55
56	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR3
57
58	write32	BBG_PMSR3_A, BBG_PMSR3_D
59
60	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR4
61
62	write32	BBG_PMSR4_A, BBG_PMSR4_D
63
64	write32	BBG_PMMR_A, BBG_PMMR_D_PMSRG
65
66	write32	BBG_PMSRG_A, BBG_PMSRG_D
67
68	/* cpg_setting */
69	write32	FRQCR_A, FRQCR_D
70
71	write32	DLLCSR_A, DLLCSR_D
72
73	nop
74	nop
75	nop
76	nop
77	nop
78	nop
79	nop
80	nop
81	nop
82	nop
83
84	/* wait 200us */
85	mov.l	REPEAT0_R3, r3
86	mov	#0, r2
87repeat0:
88	add	#1, r2
89	cmp/hs	r3, r2
90	bf	repeat0
91	nop
92
93	/* bsc_setting */
94	write32	MMSELR_A, MMSELR_D
95
96	write32	BCR_A, BCR_D
97
98	write32	CS0BCR_A, CS0BCR_D
99
100	write32	CS1BCR_A, CS1BCR_D
101
102	write32	CS2BCR_A, CS2BCR_D
103
104	write32	CS4BCR_A, CS4BCR_D
105
106	write32	CS5BCR_A, CS5BCR_D
107
108	write32	CS6BCR_A, CS6BCR_D
109
110	write32	CS0WCR_A, CS0WCR_D
111
112	write32	CS1WCR_A, CS1WCR_D
113
114	write32	CS2WCR_A, CS2WCR_D
115
116	write32	CS4WCR_A, CS4WCR_D
117
118	write32	CS5WCR_A, CS5WCR_D
119
120	write32	CS6WCR_A, CS6WCR_D
121
122	write32	CS5PCR_A, CS5PCR_D
123
124	write32	CS6PCR_A, CS6PCR_D
125
126	/* ddr_setting */
127	/* wait 200us */
128	mov.l	REPEAT0_R3, r3
129	mov	#0, r2
130repeat1:
131	add	#1, r2
132	cmp/hs	r3, r2
133	bf	repeat1
134	nop
135
136	mov.l	MIM_U_A, r0
137	mov.l	MIM_U_D, r1
138	synco
139	mov.l	r1, @r0
140	synco
141
142	mov.l	MIM_L_A, r0
143	mov.l	MIM_L_D0, r1
144	synco
145	mov.l	r1, @r0
146	synco
147
148	mov.l	STR_L_A, r0
149	mov.l	STR_L_D, r1
150	synco
151	mov.l	r1, @r0
152	synco
153
154	mov.l	SDR_L_A, r0
155	mov.l	SDR_L_D, r1
156	synco
157	mov.l	r1, @r0
158	synco
159
160	nop
161	nop
162	nop
163	nop
164
165	mov.l	SCR_L_A, r0
166	mov.l	SCR_L_D0, r1
167	synco
168	mov.l	r1, @r0
169	synco
170
171	mov.l	SCR_L_A, r0
172	mov.l	SCR_L_D1, r1
173	synco
174	mov.l	r1, @r0
175	synco
176
177	nop
178	nop
179	nop
180
181	mov.l	EMRS_A, r0
182	mov.l	EMRS_D, r1
183	synco
184	mov.l	r1, @r0
185	synco
186
187	nop
188	nop
189	nop
190
191	mov.l	MRS1_A, r0
192	mov.l	MRS1_D, r1
193	synco
194	mov.l	r1, @r0
195	synco
196
197	nop
198	nop
199	nop
200
201	mov.l	SCR_L_A, r0
202	mov.l	SCR_L_D2, r1
203	synco
204	mov.l	r1, @r0
205	synco
206
207	nop
208	nop
209	nop
210
211	mov.l	SCR_L_A, r0
212	mov.l	SCR_L_D3, r1
213	synco
214	mov.l	r1, @r0
215	synco
216
217	nop
218	nop
219	nop
220
221	mov.l	SCR_L_A, r0
222	mov.l	SCR_L_D4, r1
223	synco
224	mov.l	r1, @r0
225	synco
226
227	nop
228	nop
229	nop
230
231	mov.l	MRS2_A, r0
232	mov.l	MRS2_D, r1
233	synco
234	mov.l	r1, @r0
235	synco
236
237	nop
238	nop
239	nop
240
241	mov.l	SCR_L_A, r0
242	mov.l	SCR_L_D5, r1
243	synco
244	mov.l	r1, @r0
245	synco
246
247	/* wait 200us */
248	mov.l	REPEAT0_R1, r3
249	mov	#0, r2
250repeat2:
251	add	#1, r2
252	cmp/hs	r3, r2
253	bf	repeat2
254
255	synco
256
257	mov.l	MIM_L_A, r0
258	mov.l	MIM_L_D1, r1
259	synco
260	mov.l	r1, @r0
261	synco
262
263	rts
264	nop
265	.align	4
266
267RWTCSR_D_1:		.word	0xA507
268RWTCSR_D_2:		.word	0xA507
269RWTCNT_D:		.word	0x5A00
270	.align	2
271
272BBG_PMMR_A:		.long	0xFF800010
273BBG_PMSR1_A:		.long	0xFF800014
274BBG_PMSR2_A:		.long	0xFF800018
275BBG_PMSR3_A:		.long	0xFF80001C
276BBG_PMSR4_A:		.long	0xFF800020
277BBG_PMSRG_A:		.long	0xFF800024
278
279BBG_PMMR_D_PMSR1:	.long	0xffffbffd
280BBG_PMSR1_D:		.long	0x00004002
281BBG_PMMR_D_PMSR2:	.long	0xfc21a7ff
282BBG_PMSR2_D:		.long	0x03de5800
283BBG_PMMR_D_PMSR3:	.long	0xfffffff8
284BBG_PMSR3_D:		.long	0x00000007
285BBG_PMMR_D_PMSR4:	.long	0xdffdfff9
286BBG_PMSR4_D:		.long	0x20020006
287BBG_PMMR_D_PMSRG:	.long	0xffffffff
288BBG_PMSRG_D:		.long	0x00000000
289
290FRQCR_A:		.long	FRQCR
291DLLCSR_A:		.long	0xffc40010
292FRQCR_D:		.long	0x40233035
293DLLCSR_D:		.long	0x00000000
294
295/* for DDR-SDRAM */
296MIM_U_A:		.long	MIM_1
297MIM_L_A:		.long	MIM_2
298SCR_U_A:		.long	SCR_1
299SCR_L_A:		.long	SCR_2
300STR_U_A:		.long	STR_1
301STR_L_A:		.long	STR_2
302SDR_U_A:		.long	SDR_1
303SDR_L_A:		.long	SDR_2
304
305EMRS_A:			.long	0xFEC02000
306MRS1_A:			.long	0xFEC00B08
307MRS2_A:			.long	0xFEC00308
308
309MIM_U_D:		.long	0x00004000
310MIM_L_D0:		.long	0x03e80009
311MIM_L_D1:		.long	0x03e80209
312SCR_L_D0:		.long	0x3
313SCR_L_D1:		.long	0x2
314SCR_L_D2:		.long	0x2
315SCR_L_D3:		.long	0x4
316SCR_L_D4:		.long	0x4
317SCR_L_D5:		.long	0x0
318STR_L_D:		.long	0x000f0000
319SDR_L_D:		.long	0x00000400
320EMRS_D:			.long	0x0
321MRS1_D:			.long	0x0
322MRS2_D:			.long	0x0
323
324/* Cache Controller */
325CCR_A:			.long	CCR
326MMUCR_A:		.long	MMUCR
327RWTCNT_A:		.long	WTCNT
328
329CCR_D:			.long	0x0000090b
330CCR_D_2:		.long	0x00000103
331MMUCR_D:		.long	0x00000004
332MSTPCR0_D:		.long	0x00001001
333MSTPCR2_D:		.long	0xffffffff
334
335/* local Bus State Controller */
336MMSELR_A:		.long	MMSELR
337BCR_A:			.long	BCR
338CS0BCR_A:		.long	CS0BCR
339CS1BCR_A:		.long	CS1BCR
340CS2BCR_A:		.long	CS2BCR
341CS4BCR_A:		.long	CS4BCR
342CS5BCR_A:		.long	CS5BCR
343CS6BCR_A:		.long	CS6BCR
344CS0WCR_A:		.long	CS0WCR
345CS1WCR_A:		.long	CS1WCR
346CS2WCR_A:		.long	CS2WCR
347CS4WCR_A:		.long	CS4WCR
348CS5WCR_A:		.long	CS5WCR
349CS6WCR_A:		.long	CS6WCR
350CS5PCR_A:		.long	CS5PCR
351CS6PCR_A:		.long	CS6PCR
352
353MMSELR_D:		.long	0xA5A50003
354BCR_D:			.long	0x00000000
355CS0BCR_D:		.long	0x77777770
356CS1BCR_D:		.long	0x77777670
357CS2BCR_D:		.long	0x77777770
358CS4BCR_D:		.long	0x77777770
359CS5BCR_D:		.long	0x77777670
360CS6BCR_D:		.long	0x77777770
361CS0WCR_D:		.long	0x00020006
362CS1WCR_D:		.long	0x00232304
363CS2WCR_D:		.long	0x7777770F
364CS4WCR_D:		.long	0x7777770F
365CS5WCR_D:		.long	0x00101006
366CS6WCR_D:		.long	0x77777703
367CS5PCR_D:		.long	0x77000000
368CS6PCR_D:		.long	0x77000000
369
370REPEAT0_R3:		.long	0x00002000
371REPEAT0_R1:		.long	0x0000200
372