xref: /openbmc/u-boot/board/renesas/r2dplus/r2dplus.c (revision ea0364f1)
1 /*
2  * Copyright (C) 2007,2008
3  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 #include <common.h>
25 #include <ide.h>
26 #include <netdev.h>
27 #include <asm/processor.h>
28 #include <asm/io.h>
29 #include <asm/pci.h>
30 
31 int checkboard(void)
32 {
33 	puts("BOARD: Renesas Solutions R2D Plus\n");
34 	return 0;
35 }
36 
37 int board_init(void)
38 {
39 	return 0;
40 }
41 
42 int dram_init(void)
43 {
44 	DECLARE_GLOBAL_DATA_PTR;
45 
46 	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
47 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
48 	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
49 	return 0;
50 }
51 
52 int board_late_init(void)
53 {
54 	return 0;
55 }
56 
57 #define FPGA_BASE		0xA4000000
58 #define FPGA_CFCTL		(FPGA_BASE + 0x04)
59 #define CFCTL_EN		(0x432)
60 #define FPGA_CFPOW		(FPGA_BASE + 0x06)
61 #define CFPOW_ON		(0x02)
62 #define FPGA_CFCDINTCLR	(FPGA_BASE + 0x2A)
63 #define CFCDINTCLR_EN	(0x01)
64 
65 void ide_set_reset(int idereset)
66 {
67 	/* if reset = 1 IDE reset will be asserted */
68 	if (idereset) {
69 		outw(CFCTL_EN, FPGA_CFCTL);	/* CF enable */
70 		outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
71 		outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
72 	}
73 }
74 
75 static struct pci_controller hose;
76 void pci_init_board(void)
77 {
78 	pci_sh7751_init(&hose);
79 }
80 
81 int board_eth_init(bd_t *bis)
82 {
83 	return pci_eth_init(bis);
84 }
85