1 /* 2 * Copyright (C) 2007,2008 3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <ide.h> 10 #include <netdev.h> 11 #include <asm/processor.h> 12 #include <asm/io.h> 13 #include <asm/pci.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 int checkboard(void) 18 { 19 puts("BOARD: Renesas Solutions R2D Plus\n"); 20 return 0; 21 } 22 23 int board_init(void) 24 { 25 return 0; 26 } 27 28 int dram_init(void) 29 { 30 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 31 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 32 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); 33 return 0; 34 } 35 36 int board_late_init(void) 37 { 38 return 0; 39 } 40 41 #define FPGA_BASE 0xA4000000 42 #define FPGA_CFCTL (FPGA_BASE + 0x04) 43 #define CFCTL_EN (0x432) 44 #define FPGA_CFPOW (FPGA_BASE + 0x06) 45 #define CFPOW_ON (0x02) 46 #define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) 47 #define CFCDINTCLR_EN (0x01) 48 49 void ide_set_reset(int idereset) 50 { 51 /* if reset = 1 IDE reset will be asserted */ 52 if (idereset) { 53 outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */ 54 outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */ 55 outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */ 56 } 57 } 58 59 static struct pci_controller hose; 60 void pci_init_board(void) 61 { 62 pci_sh7751_init(&hose); 63 } 64 65 int board_eth_init(bd_t *bis) 66 { 67 return pci_eth_init(bis); 68 } 69