1/*
2 * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
3 * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
4 * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5*/
6
7#include <config.h>
8#include <version.h>
9
10#include <asm/processor.h>
11
12	.global lowlevel_init
13	.text
14	.align	2
15
16lowlevel_init:
17
18	mov.l	CCR_A, r1
19	mov.l	CCR_D_D, r0
20	mov.l	r0, @r1
21
22	mov.l	MMUCR_A, r1
23	mov.l	MMUCR_D, r0
24	mov.l	r0, @r1
25
26	mov.l	BCR1_A, r1
27	mov.l	BCR1_D, r0
28	mov.l	r0, @r1
29
30	mov.l	BCR2_A, r1
31	mov.l	BCR2_D, r0
32	mov.w	r0, @r1
33
34	mov.l	BCR3_A, r1
35	mov.l	BCR3_D, r0
36	mov.w	r0, @r1
37
38	mov.l	BCR4_A, r1
39	mov.l	BCR4_D, r0
40	mov.l	r0, @r1
41
42	mov.l	WCR1_A, r1
43	mov.l	WCR1_D, r0
44	mov.l	r0, @r1
45
46	mov.l	WCR2_A, r1
47	mov.l	WCR2_D, r0
48	mov.l	r0, @r1
49
50	mov.l	WCR3_A, r1
51	mov.l	WCR3_D, r0
52	mov.l	r0, @r1
53
54	mov.l	PCR_A, r1
55	mov.l	PCR_D, r0
56	mov.w	r0, @r1
57
58	mov.l	LED_A, r1
59	mov	#0xff, r0
60	mov.w	r0, @r1
61
62	mov.l	MCR_A, r1
63	mov.l	MCR_D1, r0
64	mov.l	r0, @r1
65
66	mov.l	RTCNT_A, r1
67	mov.l	RTCNT_D, r0
68	mov.w	r0, @r1
69
70	mov.l	RTCOR_A, r1
71	mov.l	RTCOR_D, r0
72	mov.w	r0, @r1
73
74	mov.l	RFCR_A, r1
75	mov.l	RFCR_D, r0
76	mov.w	r0, @r1
77
78	mov.l	RTCSR_A, r1
79	mov.l	RTCSR_D, r0
80	mov.w	r0, @r1
81
82	mov.l	SDMR3_A, r1
83	mov	#0x55, r0
84	mov.b	r0, @r1
85
86	/* Wait DRAM refresh 30 times */
87	mov.l	RFCR_A, r1
88	mov	#30, r3
891:
90	mov.w	@r1, r0
91	extu.w	r0, r2
92	cmp/hi	r3, r2
93	bf	1b
94
95	mov.l	MCR_A, r1
96	mov.l	MCR_D2, r0
97	mov.l	r0, @r1
98
99	mov.l	SDMR3_A, r1
100	mov	#0, r0
101	mov.b	r0, @r1
102
103	mov.l	IRLMASK_A, r1
104	mov.l	IRLMASK_D, r0
105	mov.l	r0, @r1
106
107	mov.l	CCR_A, r1
108	mov.l	CCR_D_E, r0
109	mov.l	r0, @r1
110
111	rts
112	nop
113
114	.align	2
115CCR_A:		.long	CCR		/* Cache Control Register */
116CCR_D_D:	.long	0x0808		/* Flush the cache, disable */
117CCR_D_E:	.long	0x8000090B
118
119FRQCR_A:	.long	FRQCR		/* FRQCR Address */
120FRQCR_D:	.long	0x00000e0a	/* 03/07/15 modify */
121BCR1_A:		.long	BCR1		/* BCR1 Address */
122BCR1_D:		.long	0x00180008
123BCR2_A:		.long	BCR2		/* BCR2 Address */
124BCR2_D:		.long	0xabe8
125BCR3_A:		.long	BCR3		/* BCR3 Address */
126BCR3_D:		.long	0x0000
127BCR4_A:		.long	BCR4		/* BCR4 Address */
128BCR4_D:		.long	0x00000010
129WCR1_A:		.long	WCR1		/* WCR1 Address */
130WCR1_D:		.long	0x33343333
131WCR2_A:		.long	WCR2		/* WCR2 Address */
132WCR2_D:		.long	0xcff86fbf
133WCR3_A:		.long	WCR3		/* WCR3 Address */
134WCR3_D:		.long	0x07777707
135LED_A:		.long	0x04000036	/* LED Address */
136RTCNT_A:	.long	RTCNT		/* RTCNT Address */
137RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
138RTCOR_A:	.long	RTCOR		/* RTCOR Address */
139RTCOR_D:	.long	0xA534		/* RTCOR Write Code */
140RTCSR_A:	.long	RTCSR		/* RTCSR Address */
141RTCSR_D:	.long	0xA510		/* RTCSR Write Code */
142SDMR3_A:	.long	0xFF9400CC	/* SDMR3 Address */
143SDMR3_D:	.long	0x55
144MCR_A:		.long	MCR		/* MCR Address */
145MCR_D1:		.long	0x081901F4	/* MRSET:'0' */
146MCR_D2:		.long	0x481901F4	/* MRSET:'1' */
147RFCR_A:		.long	RFCR		/* RFCR Address */
148RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
149PCR_A:		.long	PCR		/* PCR Address */
150PCR_D:		.long	0x0000
151MMUCR_A:	.long	MMUCR		/* MMUCCR Address */
152MMUCR_D:	.long	0x00000000	/* MMUCCR Data */
153IRLMASK_A:	.long	0xA4000000	/* IRLMASK Address */
154IRLMASK_D:	.long	0x00000000	/* IRLMASK Data */
155