1 /* 2 * board/renesas/porter/porter.c 3 * 4 * Copyright (C) 2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Cogent Embedded, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <dm.h> 13 #include <dm/platform_data/serial_sh.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/sh_sdhi.h> 23 #include <netdev.h> 24 #include <miiphy.h> 25 #include <i2c.h> 26 #include <div64.h> 27 #include "qos.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define CLK2MHZ(clk) (clk / 1000 / 1000) 32 void s_init(void) 33 { 34 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 35 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 36 u32 stc; 37 38 /* Watchdog init */ 39 writel(0xA5A5A500, &rwdt->rwtcsra); 40 writel(0xA5A5A500, &swdt->swtcsra); 41 42 /* CPU frequency setting. Set to 1.5GHz */ 43 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 44 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 45 46 /* QoS */ 47 qos_init(); 48 } 49 50 #define TMU0_MSTP125 BIT(25) 51 52 #define SD2CKCR 0xE615026C 53 #define SD_97500KHZ 0x7 54 55 int board_early_init_f(void) 56 { 57 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 58 59 /* 60 * SD0 clock is set to 97.5MHz by default. 61 * Set SD2 to the 97.5MHz as well. 62 */ 63 writel(SD_97500KHZ, SD2CKCR); 64 65 return 0; 66 } 67 68 #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ 69 70 int board_init(void) 71 { 72 /* adress of boot parameters */ 73 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 74 75 /* Force ethernet PHY out of reset */ 76 gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 77 gpio_direction_output(ETHERNET_PHY_RESET, 0); 78 mdelay(10); 79 gpio_direction_output(ETHERNET_PHY_RESET, 1); 80 81 return 0; 82 } 83 84 int dram_init(void) 85 { 86 if (fdtdec_setup_memory_size() != 0) 87 return -EINVAL; 88 89 return 0; 90 } 91 92 int dram_init_banksize(void) 93 { 94 fdtdec_setup_memory_banksize(); 95 96 return 0; 97 } 98 99 /* porter has KSZ8041RNLI */ 100 #define PHY_CONTROL1 0x1E 101 #define PHY_LED_MODE 0xC0000 102 #define PHY_LED_MODE_ACK 0x4000 103 int board_phy_config(struct phy_device *phydev) 104 { 105 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 106 ret &= ~PHY_LED_MODE; 107 ret |= PHY_LED_MODE_ACK; 108 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 109 110 return 0; 111 } 112 113 const struct rmobile_sysinfo sysinfo = { 114 CONFIG_ARCH_RMOBILE_BOARD_STRING 115 }; 116 117 void reset_cpu(ulong addr) 118 { 119 struct udevice *dev; 120 const u8 pmic_bus = 6; 121 const u8 pmic_addr = 0x5a; 122 u8 data; 123 int ret; 124 125 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 126 if (ret) 127 hang(); 128 129 ret = dm_i2c_read(dev, 0x13, &data, 1); 130 if (ret) 131 hang(); 132 133 data |= BIT(1); 134 135 ret = dm_i2c_write(dev, 0x13, &data, 1); 136 if (ret) 137 hang(); 138 } 139 140 #ifdef CONFIG_SPL_BUILD 141 #include <spl.h> 142 void board_init_f(ulong dummy) 143 { 144 board_early_init_f(); 145 } 146 147 void spl_board_init(void) 148 { 149 /* UART clocks enabled and gd valid - init serial console */ 150 preloader_console_init(); 151 } 152 153 void board_boot_order(u32 *spl_boot_list) 154 { 155 /* Boot from SPI NOR with YMODEM UART fallback. */ 156 spl_boot_list[0] = BOOT_DEVICE_SPI; 157 spl_boot_list[1] = BOOT_DEVICE_UART; 158 spl_boot_list[2] = BOOT_DEVICE_NONE; 159 } 160 #endif 161