1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * board/renesas/lager/lager_spl.c 4 * 5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8 #include <common.h> 9 #include <malloc.h> 10 #include <dm/platform_data/serial_sh.h> 11 #include <asm/processor.h> 12 #include <asm/mach-types.h> 13 #include <asm/io.h> 14 #include <linux/errno.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/rmobile.h> 18 #include <asm/arch/rcar-mstp.h> 19 20 #include <spl.h> 21 22 #define TMU0_MSTP125 BIT(25) 23 #define SCIF0_MSTP721 BIT(21) 24 #define QSPI_MSTP917 BIT(17) 25 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 28 29 struct reg_config { 30 u16 off; 31 u32 val; 32 }; 33 34 static void dbsc_wait(u16 reg) 35 { 36 static const u32 dbsc3_0_base = DBSC3_0_BASE; 37 38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) 39 ; 40 } 41 42 static void spl_init_sys(void) 43 { 44 u32 r0 = 0; 45 46 writel(0xa5a5a500, 0xe6020004); 47 writel(0xa5a5a500, 0xe6030004); 48 49 asm volatile( 50 /* ICIALLU - Invalidate I$ to PoU */ 51 "mcr 15, 0, %0, cr7, cr5, 0 \n" 52 /* BPIALL - Invalidate branch predictors */ 53 "mcr 15, 0, %0, cr7, cr5, 6 \n" 54 /* Set SCTLR[IZ] */ 55 "mrc 15, 0, %0, cr1, cr0, 0 \n" 56 "orr %0, #0x1800 \n" 57 "mcr 15, 0, %0, cr1, cr0, 0 \n" 58 "isb sy \n" 59 :"=r"(r0)); 60 } 61 62 static void spl_init_pfc(void) 63 { 64 static const struct reg_config pfc_with_unlock[] = { 65 { 0x0090, 0x00000000 }, 66 { 0x0094, 0x00000000 }, 67 { 0x0098, 0xc0000000 }, 68 { 0x0020, 0x00000000 }, 69 { 0x0024, 0x00000000 }, 70 { 0x0028, 0x00000000 }, 71 { 0x002c, 0x20000000 }, 72 { 0x0030, 0x00001249 }, 73 { 0x0034, 0x00000278 }, 74 { 0x0038, 0x00000841 }, 75 { 0x003c, 0x00000000 }, 76 { 0x0040, 0x00000000 }, 77 { 0x0044, 0x10000000 }, 78 { 0x0048, 0x00000001 }, 79 { 0x004c, 0x0004aab0 }, 80 { 0x0050, 0x37301b00 }, 81 { 0x0054, 0x00048da3 }, 82 { 0x0058, 0x089044a1 }, 83 { 0x005c, 0x2a3a55b4 }, 84 { 0x0160, 0x00000003 }, 85 { 0x0004, 0xffffffff }, 86 { 0x0008, 0x2aef3fff }, 87 { 0x000c, 0x3fffffff }, 88 { 0x0010, 0xff7fc07f }, 89 { 0x0014, 0x7f3ff3f8 }, 90 { 0x0018, 0x1cfdfff7 }, 91 }; 92 93 static const struct reg_config pfc_without_unlock[] = { 94 { 0x0100, 0x1fffffff }, 95 { 0x0104, 0xffff0318 }, 96 { 0x0108, 0x387fffe1 }, 97 { 0x010c, 0x00803f80 }, 98 { 0x0110, 0x1520009f }, 99 { 0x0114, 0x00000000 }, 100 { 0x0118, 0x00000000 }, 101 }; 102 103 static const u32 pfc_base = 0xe6060000; 104 105 unsigned int i; 106 107 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { 108 writel(~pfc_with_unlock[i].val, pfc_base); 109 writel(pfc_with_unlock[i].val, 110 pfc_base | pfc_with_unlock[i].off); 111 } 112 113 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) 114 writel(pfc_without_unlock[i].val, 115 pfc_base | pfc_without_unlock[i].off); 116 } 117 118 static void spl_init_gpio(void) 119 { 120 static const u16 gpio_offs[] = { 121 0x1000, 0x3000, 0x4000, 0x5000 122 }; 123 124 static const struct reg_config gpio_set[] = { 125 { 0x4000, 0x00c00000 }, 126 { 0x5000, 0x63020000 }, 127 }; 128 129 static const struct reg_config gpio_clr[] = { 130 { 0x1000, 0x00000000 }, 131 { 0x3000, 0x00000000 }, 132 { 0x4000, 0x00c00000 }, 133 { 0x5000, 0xe3020000 }, 134 }; 135 136 static const u32 gpio_base = 0xe6050000; 137 138 unsigned int i; 139 140 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 141 writel(0, gpio_base | 0x20 | gpio_offs[i]); 142 143 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 144 writel(0, gpio_base | 0x00 | gpio_offs[i]); 145 146 for (i = 0; i < ARRAY_SIZE(gpio_set); i++) 147 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); 148 149 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) 150 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); 151 } 152 153 static void spl_init_lbsc(void) 154 { 155 static const struct reg_config lbsc_config[] = { 156 { 0x00, 0x00000020 }, 157 { 0x08, 0x00002020 }, 158 { 0x30, 0x02150326 }, 159 { 0x38, 0x077f077f }, 160 }; 161 162 static const u16 lbsc_offs[] = { 163 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 164 }; 165 166 static const u32 lbsc_base = 0xfec00200; 167 168 unsigned int i; 169 170 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { 171 writel(lbsc_config[i].val, 172 lbsc_base | lbsc_config[i].off); 173 writel(lbsc_config[i].val, 174 lbsc_base | (lbsc_config[i].off + 4)); 175 } 176 177 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) 178 writel(0, lbsc_base | lbsc_offs[i]); 179 } 180 181 static void spl_init_dbsc(void) 182 { 183 static const struct reg_config dbsc_config1[] = { 184 { 0x0018, 0x21000000 }, 185 { 0x0018, 0x11000000 }, 186 { 0x0018, 0x10000000 }, 187 { 0x0280, 0x0000a55a }, 188 { 0x0290, 0x00000001 }, 189 { 0x02a0, 0x80000000 }, 190 { 0x0290, 0x00000004 }, 191 }; 192 193 static const struct reg_config dbsc_config4[] = { 194 { 0x0290, 0x00000010 }, 195 { 0x02a0, 0xf004649b }, 196 { 0x0290, 0x0000000f }, 197 { 0x02a0, 0x00181ee4 }, 198 { 0x0290, 0x00000060 }, 199 { 0x02a0, 0x330657b2 }, 200 { 0x0290, 0x00000001 }, 201 { 0x02a0, 0x00000071 }, 202 { 0x0020, 0x00000007 }, 203 { 0x0024, 0x10030a02 }, 204 { 0x0030, 0x00000001 }, 205 { 0x00b0, 0x00000000 }, 206 { 0x0040, 0x0000000b }, 207 { 0x0044, 0x00000008 }, 208 { 0x0048, 0x00000000 }, 209 { 0x0050, 0x0000000b }, 210 { 0x0054, 0x000c000b }, 211 { 0x0058, 0x00000027 }, 212 { 0x005c, 0x0000001c }, 213 { 0x0060, 0x00000005 }, 214 { 0x0064, 0x00000018 }, 215 { 0x0068, 0x00000008 }, 216 { 0x006c, 0x0000000c }, 217 { 0x0070, 0x00000009 }, 218 { 0x0074, 0x00000012 }, 219 { 0x0078, 0x000000d0 }, 220 { 0x007c, 0x00140005 }, 221 { 0x0080, 0x00050004 }, 222 { 0x0084, 0x70233005 }, 223 { 0x0088, 0x000c0000 }, 224 { 0x008c, 0x00000300 }, 225 { 0x0090, 0x00000040 }, 226 { 0x0100, 0x00000001 }, 227 { 0x00c0, 0x00020001 }, 228 { 0x00c8, 0x20082008 }, 229 { 0x0380, 0x00020002 }, 230 { 0x0390, 0x0000000f }, 231 }; 232 233 static const struct reg_config dbsc_config5[] = { 234 { 0x0244, 0x00000011 }, 235 { 0x0290, 0x00000006 }, 236 { 0x02a0, 0x0005c000 }, 237 { 0x0290, 0x00000003 }, 238 { 0x02a0, 0x0300c481 }, 239 { 0x0290, 0x00000023 }, 240 { 0x02a0, 0x00fdb6c0 }, 241 { 0x0290, 0x00000011 }, 242 { 0x02a0, 0x1000040b }, 243 { 0x0290, 0x00000012 }, 244 { 0x02a0, 0x9d5cbb66 }, 245 { 0x0290, 0x00000013 }, 246 { 0x02a0, 0x1a868300 }, 247 { 0x0290, 0x00000014 }, 248 { 0x02a0, 0x300214d8 }, 249 { 0x0290, 0x00000015 }, 250 { 0x02a0, 0x00000d70 }, 251 { 0x0290, 0x00000016 }, 252 { 0x02a0, 0x00000006 }, 253 { 0x0290, 0x00000017 }, 254 { 0x02a0, 0x00000018 }, 255 { 0x0290, 0x0000001a }, 256 { 0x02a0, 0x910035c7 }, 257 { 0x0290, 0x00000004 }, 258 }; 259 260 static const struct reg_config dbsc_config6[] = { 261 { 0x0290, 0x00000001 }, 262 { 0x02a0, 0x00000181 }, 263 { 0x0018, 0x11000000 }, 264 { 0x0290, 0x00000004 }, 265 }; 266 267 static const struct reg_config dbsc_config7[] = { 268 { 0x0290, 0x00000001 }, 269 { 0x02a0, 0x0000fe01 }, 270 { 0x0290, 0x00000004 }, 271 }; 272 273 static const struct reg_config dbsc_config8[] = { 274 { 0x0304, 0x00000000 }, 275 { 0x00f4, 0x01004c20 }, 276 { 0x00f8, 0x014000aa }, 277 { 0x00e0, 0x00000140 }, 278 { 0x00e4, 0x00081860 }, 279 { 0x00e8, 0x00010000 }, 280 { 0x0014, 0x00000001 }, 281 { 0x0010, 0x00000001 }, 282 { 0x0280, 0x00000000 }, 283 }; 284 285 static const u32 dbsc3_0_base = DBSC3_0_BASE; 286 unsigned int i; 287 288 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) 289 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); 290 291 dbsc_wait(0x2a0); 292 293 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) 294 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); 295 296 dbsc_wait(0x240); 297 298 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) 299 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); 300 301 dbsc_wait(0x2a0); 302 303 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) 304 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); 305 306 dbsc_wait(0x2a0); 307 308 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) 309 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); 310 311 dbsc_wait(0x2a0); 312 313 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) 314 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); 315 316 } 317 318 static void spl_init_qspi(void) 319 { 320 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 321 322 static const u32 qspi_base = 0xe6b10000; 323 324 writeb(0x08, qspi_base + 0x00); 325 writeb(0x00, qspi_base + 0x01); 326 writeb(0x06, qspi_base + 0x02); 327 writeb(0x01, qspi_base + 0x0a); 328 writeb(0x00, qspi_base + 0x0b); 329 writeb(0x00, qspi_base + 0x0c); 330 writeb(0x00, qspi_base + 0x0d); 331 writeb(0x00, qspi_base + 0x0e); 332 333 writew(0xe080, qspi_base + 0x10); 334 335 writeb(0xc0, qspi_base + 0x18); 336 writeb(0x00, qspi_base + 0x18); 337 writeb(0x00, qspi_base + 0x08); 338 writeb(0x48, qspi_base + 0x00); 339 } 340 341 void board_init_f(ulong dummy) 342 { 343 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 344 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 345 346 /* 347 * SD0 clock is set to 97.5MHz by default. 348 * Set SD2 to the 97.5MHz as well. 349 */ 350 writel(SD_97500KHZ, SD2CKCR); 351 352 spl_init_sys(); 353 spl_init_pfc(); 354 spl_init_gpio(); 355 spl_init_lbsc(); 356 spl_init_dbsc(); 357 spl_init_qspi(); 358 } 359 360 void spl_board_init(void) 361 { 362 /* UART clocks enabled and gd valid - init serial console */ 363 preloader_console_init(); 364 } 365 366 void board_boot_order(u32 *spl_boot_list) 367 { 368 const u32 jtag_magic = 0x1337c0de; 369 const u32 load_magic = 0xb33fc0de; 370 371 /* 372 * If JTAG probe sets special word at 0xe6300020, then it must 373 * put U-Boot into RAM and SPL will start it from RAM. 374 */ 375 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { 376 printf("JTAG boot detected!\n"); 377 378 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) 379 ; 380 381 spl_boot_list[0] = BOOT_DEVICE_RAM; 382 spl_boot_list[1] = BOOT_DEVICE_NONE; 383 384 return; 385 } 386 387 /* Boot from SPI NOR with YMODEM UART fallback. */ 388 spl_boot_list[0] = BOOT_DEVICE_SPI; 389 spl_boot_list[1] = BOOT_DEVICE_UART; 390 spl_boot_list[2] = BOOT_DEVICE_NONE; 391 } 392 393 void reset_cpu(ulong addr) 394 { 395 } 396