1 /* 2 * board/renesas/lager/lager.c 3 * This file is lager board support. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <netdev.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <asm/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <miiphy.h> 22 #include <i2c.h> 23 #include "qos.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define CLK2MHZ(clk) (clk / 1000 / 1000) 28 void s_init(void) 29 { 30 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 31 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 32 33 /* Watchdog init */ 34 writel(0xA5A5A500, &rwdt->rwtcsra); 35 writel(0xA5A5A500, &swdt->swtcsra); 36 37 /* CPU frequency setting. Set to 1.4GHz */ 38 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { 39 u32 stat = 0; 40 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) 41 << PLL0_STC_BIT; 42 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 43 44 do { 45 stat = readl(PLLECR) & PLL0ST; 46 } while (stat == 0x0); 47 } 48 49 /* QoS(Quality-of-Service) Init */ 50 qos_init(); 51 } 52 53 #define MSTPSR1 0xE6150038 54 #define SMSTPCR1 0xE6150134 55 #define TMU0_MSTP125 (1 << 25) 56 57 #define MSTPSR7 0xE61501C4 58 #define SMSTPCR7 0xE615014C 59 #define SCIF0_MSTP721 (1 << 21) 60 61 #define MSTPSR8 0xE61509A0 62 #define SMSTPCR8 0xE6150990 63 #define ETHER_MSTP813 (1 << 13) 64 65 #define mstp_setbits(type, addr, saddr, set) \ 66 out_##type((saddr), in_##type(addr) | (set)) 67 #define mstp_clrbits(type, addr, saddr, clear) \ 68 out_##type((saddr), in_##type(addr) & ~(clear)) 69 #define mstp_setbits_le32(addr, saddr, set) \ 70 mstp_setbits(le32, addr, saddr, set) 71 #define mstp_clrbits_le32(addr, saddr, clear) \ 72 mstp_clrbits(le32, addr, saddr, clear) 73 74 int board_early_init_f(void) 75 { 76 /* TMU0 */ 77 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 78 /* SCIF0 */ 79 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 80 /* ETHER */ 81 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 82 83 return 0; 84 } 85 86 void arch_preboot_os(void) 87 { 88 /* Disable TMU0 */ 89 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 90 } 91 92 DECLARE_GLOBAL_DATA_PTR; 93 int board_init(void) 94 { 95 /* adress of boot parameters */ 96 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 97 98 /* Init PFC controller */ 99 r8a7790_pinmux_init(); 100 101 /* ETHER Enable */ 102 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 103 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 104 gpio_request(GPIO_FN_ETH_RXD0, NULL); 105 gpio_request(GPIO_FN_ETH_RXD1, NULL); 106 gpio_request(GPIO_FN_ETH_LINK, NULL); 107 gpio_request(GPIO_FN_ETH_REF_CLK, NULL); 108 gpio_request(GPIO_FN_ETH_MDIO, NULL); 109 gpio_request(GPIO_FN_ETH_TXD1, NULL); 110 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 111 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 112 gpio_request(GPIO_FN_ETH_TXD0, NULL); 113 gpio_request(GPIO_FN_ETH_MDC, NULL); 114 gpio_request(GPIO_FN_IRQ0, NULL); 115 116 gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ 117 gpio_direction_output(GPIO_GP_5_31, 0); 118 mdelay(20); 119 gpio_set_value(GPIO_GP_5_31, 1); 120 udelay(1); 121 122 return 0; 123 } 124 125 #define CXR24 0xEE7003C0 /* MAC address high register */ 126 #define CXR25 0xEE7003C8 /* MAC address low register */ 127 int board_eth_init(bd_t *bis) 128 { 129 int ret = -ENODEV; 130 131 #ifdef CONFIG_SH_ETHER 132 u32 val; 133 unsigned char enetaddr[6]; 134 135 ret = sh_eth_initialize(bis); 136 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 137 return ret; 138 139 /* Set Mac address */ 140 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 141 enetaddr[2] << 8 | enetaddr[3]; 142 writel(val, CXR24); 143 144 val = enetaddr[4] << 8 | enetaddr[5]; 145 writel(val, CXR25); 146 147 #endif 148 149 return ret; 150 } 151 152 /* lager has KSZ8041NL/RNL */ 153 #define PHY_CONTROL1 0x1E 154 #define PHY_LED_MODE 0xC0000 155 #define PHY_LED_MODE_ACK 0x4000 156 int board_phy_config(struct phy_device *phydev) 157 { 158 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 159 ret &= ~PHY_LED_MODE; 160 ret |= PHY_LED_MODE_ACK; 161 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 162 163 return 0; 164 } 165 166 int dram_init(void) 167 { 168 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 169 170 return 0; 171 } 172 173 const struct rmobile_sysinfo sysinfo = { 174 CONFIG_RMOBILE_BOARD_STRING 175 }; 176 177 void reset_cpu(ulong addr) 178 { 179 u8 val; 180 181 i2c_set_bus_num(3); /* PowerIC connected to ch3 */ 182 i2c_init(400000, 0); 183 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 184 val |= 0x02; 185 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 186 } 187