1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * board/renesas/lager/lager.c 4 * This file is lager board support. 5 * 6 * Copyright (C) 2013 Renesas Electronics Corporation 7 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 8 */ 9 10 #include <common.h> 11 #include <environment.h> 12 #include <malloc.h> 13 #include <netdev.h> 14 #include <dm.h> 15 #include <dm/platform_data/serial_sh.h> 16 #include <asm/processor.h> 17 #include <asm/mach-types.h> 18 #include <asm/io.h> 19 #include <linux/errno.h> 20 #include <asm/arch/sys_proto.h> 21 #include <asm/gpio.h> 22 #include <asm/arch/rmobile.h> 23 #include <asm/arch/rcar-mstp.h> 24 #include <asm/arch/mmc.h> 25 #include <asm/arch/sh_sdhi.h> 26 #include <miiphy.h> 27 #include <i2c.h> 28 #include <mmc.h> 29 #include "qos.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define CLK2MHZ(clk) (clk / 1000 / 1000) 34 void s_init(void) 35 { 36 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 37 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 38 39 /* Watchdog init */ 40 writel(0xA5A5A500, &rwdt->rwtcsra); 41 writel(0xA5A5A500, &swdt->swtcsra); 42 43 /* CPU frequency setting. Set to 1.4GHz */ 44 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { 45 u32 stat = 0; 46 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) 47 << PLL0_STC_BIT; 48 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 49 50 do { 51 stat = readl(PLLECR) & PLL0ST; 52 } while (stat == 0x0); 53 } 54 55 /* QoS(Quality-of-Service) Init */ 56 qos_init(); 57 } 58 59 #define TMU0_MSTP125 BIT(25) 60 61 #define SD1CKCR 0xE6150078 62 #define SD2CKCR 0xE615026C 63 #define SD_97500KHZ 0x7 64 65 int board_early_init_f(void) 66 { 67 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 68 69 /* 70 * SD0 clock is set to 97.5MHz by default. 71 * Set SD1 and SD2 to the 97.5MHz as well. 72 */ 73 writel(SD_97500KHZ, SD1CKCR); 74 writel(SD_97500KHZ, SD2CKCR); 75 76 return 0; 77 } 78 79 #define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */ 80 81 int board_init(void) 82 { 83 /* adress of boot parameters */ 84 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 85 86 /* Force ethernet PHY out of reset */ 87 gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 88 gpio_direction_output(ETHERNET_PHY_RESET, 0); 89 mdelay(10); 90 gpio_direction_output(ETHERNET_PHY_RESET, 1); 91 92 return 0; 93 } 94 95 int dram_init(void) 96 { 97 if (fdtdec_setup_mem_size_base() != 0) 98 return -EINVAL; 99 100 return 0; 101 } 102 103 int dram_init_banksize(void) 104 { 105 fdtdec_setup_memory_banksize(); 106 107 return 0; 108 } 109 110 /* KSZ8041NL/RNL */ 111 #define PHY_CONTROL1 0x1E 112 #define PHY_LED_MODE 0xC000 113 #define PHY_LED_MODE_ACK 0x4000 114 int board_phy_config(struct phy_device *phydev) 115 { 116 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 117 ret &= ~PHY_LED_MODE; 118 ret |= PHY_LED_MODE_ACK; 119 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 120 121 return 0; 122 } 123 124 void reset_cpu(ulong addr) 125 { 126 struct udevice *dev; 127 const u8 pmic_bus = 2; 128 const u8 pmic_addr = 0x58; 129 u8 data; 130 int ret; 131 132 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 133 if (ret) 134 hang(); 135 136 ret = dm_i2c_read(dev, 0x13, &data, 1); 137 if (ret) 138 hang(); 139 140 data |= BIT(1); 141 142 ret = dm_i2c_write(dev, 0x13, &data, 1); 143 if (ret) 144 hang(); 145 } 146 147 enum env_location env_get_location(enum env_operation op, int prio) 148 { 149 const u32 load_magic = 0xb33fc0de; 150 151 /* Block environment access if loaded using JTAG */ 152 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 153 (op != ENVOP_INIT)) 154 return ENVL_UNKNOWN; 155 156 if (prio) 157 return ENVL_UNKNOWN; 158 159 return ENVL_SPI_FLASH; 160 } 161