1 /* 2 * board/renesas/lager/lager.c 3 * This file is lager board support. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <netdev.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <asm/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/mmc.h> 23 #include <miiphy.h> 24 #include <i2c.h> 25 #include <mmc.h> 26 #include "qos.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define CLK2MHZ(clk) (clk / 1000 / 1000) 31 void s_init(void) 32 { 33 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 34 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 35 36 /* Watchdog init */ 37 writel(0xA5A5A500, &rwdt->rwtcsra); 38 writel(0xA5A5A500, &swdt->swtcsra); 39 40 /* CPU frequency setting. Set to 1.4GHz */ 41 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { 42 u32 stat = 0; 43 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) 44 << PLL0_STC_BIT; 45 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 46 47 do { 48 stat = readl(PLLECR) & PLL0ST; 49 } while (stat == 0x0); 50 } 51 52 /* QoS(Quality-of-Service) Init */ 53 qos_init(); 54 } 55 56 #define TMU0_MSTP125 (1 << 25) 57 #define SCIF0_MSTP721 (1 << 21) 58 #define ETHER_MSTP813 (1 << 13) 59 #define MMC1_MSTP305 (1 << 5) 60 61 int board_early_init_f(void) 62 { 63 /* TMU0 */ 64 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 65 /* SCIF0 */ 66 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 67 /* ETHER */ 68 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 69 /* eMMC */ 70 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305); 71 72 return 0; 73 } 74 75 DECLARE_GLOBAL_DATA_PTR; 76 int board_init(void) 77 { 78 /* adress of boot parameters */ 79 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 80 81 /* Init PFC controller */ 82 r8a7790_pinmux_init(); 83 84 /* ETHER Enable */ 85 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 86 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 87 gpio_request(GPIO_FN_ETH_RXD0, NULL); 88 gpio_request(GPIO_FN_ETH_RXD1, NULL); 89 gpio_request(GPIO_FN_ETH_LINK, NULL); 90 gpio_request(GPIO_FN_ETH_REF_CLK, NULL); 91 gpio_request(GPIO_FN_ETH_MDIO, NULL); 92 gpio_request(GPIO_FN_ETH_TXD1, NULL); 93 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 94 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 95 gpio_request(GPIO_FN_ETH_TXD0, NULL); 96 gpio_request(GPIO_FN_ETH_MDC, NULL); 97 gpio_request(GPIO_FN_IRQ0, NULL); 98 99 gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ 100 gpio_direction_output(GPIO_GP_5_31, 0); 101 mdelay(20); 102 gpio_set_value(GPIO_GP_5_31, 1); 103 udelay(1); 104 105 return 0; 106 } 107 108 #define CXR24 0xEE7003C0 /* MAC address high register */ 109 #define CXR25 0xEE7003C8 /* MAC address low register */ 110 int board_eth_init(bd_t *bis) 111 { 112 int ret = -ENODEV; 113 114 #ifdef CONFIG_SH_ETHER 115 u32 val; 116 unsigned char enetaddr[6]; 117 118 ret = sh_eth_initialize(bis); 119 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 120 return ret; 121 122 /* Set Mac address */ 123 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 124 enetaddr[2] << 8 | enetaddr[3]; 125 writel(val, CXR24); 126 127 val = enetaddr[4] << 8 | enetaddr[5]; 128 writel(val, CXR25); 129 130 #endif 131 132 return ret; 133 } 134 135 /* lager has KSZ8041NL/RNL */ 136 #define PHY_CONTROL1 0x1E 137 #define PHY_LED_MODE 0xC0000 138 #define PHY_LED_MODE_ACK 0x4000 139 int board_phy_config(struct phy_device *phydev) 140 { 141 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 142 ret &= ~PHY_LED_MODE; 143 ret |= PHY_LED_MODE_ACK; 144 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 145 146 return 0; 147 } 148 149 int board_mmc_init(bd_t *bis) 150 { 151 int ret = 0; 152 153 #ifdef CONFIG_SH_MMCIF 154 gpio_request(GPIO_FN_MMC1_D0, NULL); 155 gpio_request(GPIO_FN_MMC1_D1, NULL); 156 gpio_request(GPIO_FN_MMC1_D2, NULL); 157 gpio_request(GPIO_FN_MMC1_D3, NULL); 158 gpio_request(GPIO_FN_MMC1_D4, NULL); 159 gpio_request(GPIO_FN_MMC1_D5, NULL); 160 gpio_request(GPIO_FN_MMC1_D6, NULL); 161 gpio_request(GPIO_FN_MMC1_D7, NULL); 162 gpio_request(GPIO_FN_MMC1_CLK, NULL); 163 gpio_request(GPIO_FN_MMC1_CMD, NULL); 164 165 ret = mmcif_mmc_init(); 166 #endif 167 return ret; 168 } 169 170 171 int dram_init(void) 172 { 173 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 174 175 return 0; 176 } 177 178 const struct rmobile_sysinfo sysinfo = { 179 CONFIG_RMOBILE_BOARD_STRING 180 }; 181 182 void reset_cpu(ulong addr) 183 { 184 u8 val; 185 186 i2c_set_bus_num(3); /* PowerIC connected to ch3 */ 187 i2c_init(400000, 0); 188 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 189 val |= 0x02; 190 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 191 } 192