1 /* 2 * board/renesas/lager/lager.c 3 * This file is lager board support. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <netdev.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <asm/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <miiphy.h> 22 #include <i2c.h> 23 #include "qos.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define CLK2MHZ(clk) (clk / 1000 / 1000) 28 void s_init(void) 29 { 30 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 31 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 32 u32 stc; 33 34 /* Watchdog init */ 35 writel(0xA5A5A500, &rwdt->rwtcsra); 36 writel(0xA5A5A500, &swdt->swtcsra); 37 38 /* CPU frequency setting. Set to 1.4GHz */ 39 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 40 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 41 42 /* QoS(Quality-of-Service) Init */ 43 qos_init(); 44 } 45 46 #define MSTPSR1 0xE6150038 47 #define SMSTPCR1 0xE6150134 48 #define TMU0_MSTP125 (1 << 25) 49 50 #define MSTPSR7 0xE61501C4 51 #define SMSTPCR7 0xE615014C 52 #define SCIF0_MSTP721 (1 << 21) 53 54 #define MSTPSR8 0xE61509A0 55 #define SMSTPCR8 0xE6150990 56 #define ETHER_MSTP813 (1 << 13) 57 58 #define mstp_setbits(type, addr, saddr, set) \ 59 out_##type((saddr), in_##type(addr) | (set)) 60 #define mstp_clrbits(type, addr, saddr, clear) \ 61 out_##type((saddr), in_##type(addr) & ~(clear)) 62 #define mstp_setbits_le32(addr, saddr, set) \ 63 mstp_setbits(le32, addr, saddr, set) 64 #define mstp_clrbits_le32(addr, saddr, clear) \ 65 mstp_clrbits(le32, addr, saddr, clear) 66 67 int board_early_init_f(void) 68 { 69 /* TMU0 */ 70 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 71 /* SCIF0 */ 72 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 73 /* ETHER */ 74 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 75 76 return 0; 77 } 78 79 void arch_preboot_os(void) 80 { 81 /* Disable TMU0 */ 82 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 83 } 84 85 DECLARE_GLOBAL_DATA_PTR; 86 int board_init(void) 87 { 88 /* adress of boot parameters */ 89 gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100; 90 91 /* Init PFC controller */ 92 r8a7790_pinmux_init(); 93 94 /* ETHER Enable */ 95 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 96 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 97 gpio_request(GPIO_FN_ETH_RXD0, NULL); 98 gpio_request(GPIO_FN_ETH_RXD1, NULL); 99 gpio_request(GPIO_FN_ETH_LINK, NULL); 100 gpio_request(GPIO_FN_ETH_REF_CLK, NULL); 101 gpio_request(GPIO_FN_ETH_MDIO, NULL); 102 gpio_request(GPIO_FN_ETH_TXD1, NULL); 103 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 104 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 105 gpio_request(GPIO_FN_ETH_TXD0, NULL); 106 gpio_request(GPIO_FN_ETH_MDC, NULL); 107 gpio_request(GPIO_FN_IRQ0, NULL); 108 109 gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ 110 gpio_direction_output(GPIO_GP_5_31, 0); 111 mdelay(20); 112 gpio_set_value(GPIO_GP_5_31, 1); 113 udelay(1); 114 115 return 0; 116 } 117 118 #define CXR24 0xEE7003C0 /* MAC address high register */ 119 #define CXR25 0xEE7003C8 /* MAC address low register */ 120 int board_eth_init(bd_t *bis) 121 { 122 int ret = -ENODEV; 123 124 #ifdef CONFIG_SH_ETHER 125 u32 val; 126 unsigned char enetaddr[6]; 127 128 ret = sh_eth_initialize(bis); 129 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 130 return ret; 131 132 /* Set Mac address */ 133 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 134 enetaddr[2] << 8 | enetaddr[3]; 135 writel(val, CXR24); 136 137 val = enetaddr[4] << 8 | enetaddr[5]; 138 writel(val, CXR25); 139 140 #endif 141 142 return ret; 143 } 144 145 /* lager has KSZ8041NL/RNL */ 146 #define PHY_CONTROL1 0x1E 147 #define PHY_LED_MODE 0xC0000 148 #define PHY_LED_MODE_ACK 0x4000 149 int board_phy_config(struct phy_device *phydev) 150 { 151 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 152 ret &= ~PHY_LED_MODE; 153 ret |= PHY_LED_MODE_ACK; 154 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 155 156 return 0; 157 } 158 159 int dram_init(void) 160 { 161 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 162 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 163 164 return 0; 165 } 166 167 const struct rmobile_sysinfo sysinfo = { 168 CONFIG_RMOBILE_BOARD_STRING 169 }; 170 171 void dram_init_banksize(void) 172 { 173 gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE; 174 gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE; 175 } 176 177 int board_late_init(void) 178 { 179 return 0; 180 } 181 182 void reset_cpu(ulong addr) 183 { 184 u8 val; 185 186 i2c_set_bus_num(3); /* PowerIC connected to ch3 */ 187 i2c_init(400000, 0); 188 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 189 val |= 0x02; 190 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 191 } 192