1 /* 2 * board/renesas/koelsch/koelsch_spl.c 3 * 4 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <dm/platform_data/serial_sh.h> 12 #include <asm/processor.h> 13 #include <asm/mach-types.h> 14 #include <asm/io.h> 15 #include <linux/errno.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/rmobile.h> 19 #include <asm/arch/rcar-mstp.h> 20 21 #include <spl.h> 22 23 #define TMU0_MSTP125 BIT(25) 24 #define SCIF0_MSTP721 BIT(21) 25 #define QSPI_MSTP917 BIT(17) 26 27 #define SD2CKCR 0xE615026C 28 #define SD_97500KHZ 0x7 29 30 struct reg_config { 31 u16 off; 32 u32 val; 33 }; 34 35 static void dbsc_wait(u16 reg) 36 { 37 static const u32 dbsc3_0_base = DBSC3_0_BASE; 38 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; 39 40 while (!(readl(dbsc3_0_base + reg) & BIT(0))) 41 ; 42 43 while (!(readl(dbsc3_1_base + reg) & BIT(0))) 44 ; 45 } 46 47 static void spl_init_sys(void) 48 { 49 u32 r0 = 0; 50 51 writel(0xa5a5a500, 0xe6020004); 52 writel(0xa5a5a500, 0xe6030004); 53 54 asm volatile( 55 /* ICIALLU - Invalidate I$ to PoU */ 56 "mcr 15, 0, %0, cr7, cr5, 0 \n" 57 /* BPIALL - Invalidate branch predictors */ 58 "mcr 15, 0, %0, cr7, cr5, 6 \n" 59 /* Set SCTLR[IZ] */ 60 "mrc 15, 0, %0, cr1, cr0, 0 \n" 61 "orr %0, #0x1800 \n" 62 "mcr 15, 0, %0, cr1, cr0, 0 \n" 63 "isb sy \n" 64 :"=r"(r0)); 65 } 66 67 static void spl_init_pfc(void) 68 { 69 static const struct reg_config pfc_with_unlock[] = { 70 { 0x0090, 0x60000000 }, 71 { 0x0094, 0x60000000 }, 72 { 0x0098, 0x00800200 }, 73 { 0x009c, 0x00000000 }, 74 { 0x0020, 0x00000000 }, 75 { 0x0024, 0x00000000 }, 76 { 0x0028, 0x000244c8 }, 77 { 0x002c, 0x00000000 }, 78 { 0x0030, 0x00002400 }, 79 { 0x0034, 0x01520000 }, 80 { 0x0038, 0x00724003 }, 81 { 0x003c, 0x00000000 }, 82 { 0x0040, 0x00000000 }, 83 { 0x0044, 0x00000000 }, 84 { 0x0048, 0x00000000 }, 85 { 0x004c, 0x00000000 }, 86 { 0x0050, 0x00000000 }, 87 { 0x0054, 0x00000000 }, 88 { 0x0058, 0x00000000 }, 89 { 0x005c, 0x00000000 }, 90 { 0x0160, 0x00000000 }, 91 { 0x0004, 0xffffffff }, 92 { 0x0008, 0x00ec3fff }, 93 { 0x000c, 0x3bc001e7 }, 94 { 0x0010, 0x5bffffff }, 95 { 0x0014, 0x1ffffffb }, 96 { 0x0018, 0x01bffff0 }, 97 { 0x001c, 0xcf7fffff }, 98 { 0x0074, 0x0381fc00 }, 99 }; 100 101 static const struct reg_config pfc_without_unlock[] = { 102 { 0x0100, 0xffffffdf }, 103 { 0x0104, 0xc883c3ff }, 104 { 0x0108, 0x1201f3c9 }, 105 { 0x010c, 0x00000000 }, 106 { 0x0110, 0xffffeb04 }, 107 { 0x0114, 0xc003ffff }, 108 { 0x0118, 0x0800000f }, 109 { 0x011c, 0x001800f0 }, 110 }; 111 112 static const u32 pfc_base = 0xe6060000; 113 114 unsigned int i; 115 116 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { 117 writel(~pfc_with_unlock[i].val, pfc_base); 118 writel(pfc_with_unlock[i].val, 119 pfc_base | pfc_with_unlock[i].off); 120 } 121 122 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) 123 writel(pfc_without_unlock[i].val, 124 pfc_base | pfc_without_unlock[i].off); 125 } 126 127 static void spl_init_gpio(void) 128 { 129 static const u16 gpio_offs[] = { 130 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 131 }; 132 133 static const struct reg_config gpio_set[] = { 134 { 0x2000, 0x04381000 }, 135 { 0x5000, 0x00000000 }, 136 { 0x5800, 0x000e0000 }, 137 138 }; 139 140 static const struct reg_config gpio_clr[] = { 141 { 0x1000, 0x00000000 }, 142 { 0x2000, 0x04381010 }, 143 { 0x3000, 0x00000000 }, 144 { 0x4000, 0x00000000 }, 145 { 0x5000, 0x00400000 }, 146 { 0x5400, 0x00000000 }, 147 { 0x5800, 0x000e0380 }, 148 }; 149 150 static const u32 gpio_base = 0xe6050000; 151 152 unsigned int i; 153 154 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 155 writel(0, gpio_base | 0x20 | gpio_offs[i]); 156 157 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 158 writel(0, gpio_base | 0x00 | gpio_offs[i]); 159 160 for (i = 0; i < ARRAY_SIZE(gpio_set); i++) 161 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); 162 163 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) 164 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); 165 } 166 167 static void spl_init_lbsc(void) 168 { 169 static const struct reg_config lbsc_config[] = { 170 { 0x00, 0x00000020 }, 171 { 0x08, 0x00002020 }, 172 { 0x30, 0x2a103320 }, 173 { 0x38, 0xff70ff70 }, 174 }; 175 176 static const u16 lbsc_offs[] = { 177 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 178 }; 179 180 static const u32 lbsc_base = 0xfec00200; 181 182 unsigned int i; 183 184 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { 185 writel(lbsc_config[i].val, 186 lbsc_base | lbsc_config[i].off); 187 writel(lbsc_config[i].val, 188 lbsc_base | (lbsc_config[i].off + 4)); 189 } 190 191 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) 192 writel(0, lbsc_base | lbsc_offs[i]); 193 } 194 195 static void spl_init_dbsc(void) 196 { 197 static const struct reg_config dbsc_config1[] = { 198 { 0x0018, 0x21000000 }, 199 { 0x0018, 0x11000000 }, 200 { 0x0018, 0x10000000 }, 201 { 0x0280, 0x0000a55a }, 202 { 0x0290, 0x00000010 }, 203 { 0x02a0, 0xf004649b }, 204 { 0x0020, 0x00000007 }, 205 { 0x0024, 0x0f030a02 }, 206 { 0x0030, 0x00000001 }, 207 { 0x00b0, 0x00000000 }, 208 { 0x0040, 0x0000000b }, 209 { 0x0044, 0x00000008 }, 210 { 0x0048, 0x00000000 }, 211 { 0x0050, 0x0000000b }, 212 { 0x0054, 0x000c000b }, 213 { 0x0058, 0x00000027 }, 214 { 0x005c, 0x0000001c }, 215 { 0x0060, 0x00000006 }, 216 { 0x0064, 0x00000020 }, 217 { 0x0068, 0x00000008 }, 218 { 0x006c, 0x0000000c }, 219 { 0x0070, 0x00000009 }, 220 { 0x0074, 0x00000012 }, 221 { 0x0078, 0x000000d0 }, 222 { 0x007c, 0x00140005 }, 223 { 0x0080, 0x00050004 }, 224 { 0x0084, 0x70233005 }, 225 { 0x0088, 0x000c0000 }, 226 { 0x008c, 0x00000300 }, 227 { 0x0090, 0x00000040 }, 228 { 0x0100, 0x00000001 }, 229 { 0x00c0, 0x00020001 }, 230 { 0x00c8, 0x20082008 }, 231 { 0x0380, 0x00020002 }, 232 { 0x0390, 0x0000001f }, 233 }; 234 235 static const struct reg_config dbsc_config5[] = { 236 { 0x0244, 0x00000011 }, 237 { 0x0290, 0x00000006 }, 238 { 0x02a0, 0x0005c000 }, 239 { 0x0290, 0x00000003 }, 240 { 0x02a0, 0x0300c481 }, 241 { 0x0290, 0x00000023 }, 242 { 0x02a0, 0x00fdb6c0 }, 243 { 0x0290, 0x00000011 }, 244 { 0x02a0, 0x1000040b }, 245 { 0x0290, 0x00000012 }, 246 { 0x02a0, 0x9d9cbb66 }, 247 { 0x0290, 0x00000013 }, 248 { 0x02a0, 0x1a868400 }, 249 { 0x0290, 0x00000014 }, 250 { 0x02a0, 0x300214d8 }, 251 { 0x0290, 0x00000015 }, 252 { 0x02a0, 0x00000d70 }, 253 { 0x0290, 0x00000016 }, 254 { 0x02a0, 0x00000006 }, 255 { 0x0290, 0x00000017 }, 256 { 0x02a0, 0x00000018 }, 257 { 0x0290, 0x0000001a }, 258 { 0x02a0, 0x910035c7 }, 259 { 0x0290, 0x00000004 }, 260 }; 261 262 static const struct reg_config dbsc_config6[] = { 263 { 0x0290, 0x00000001 }, 264 { 0x02a0, 0x00000181 }, 265 { 0x0018, 0x11000000 }, 266 { 0x0290, 0x00000004 }, 267 }; 268 269 static const struct reg_config dbsc_config7[] = { 270 { 0x0290, 0x00000001 }, 271 { 0x02a0, 0x0000fe01 }, 272 { 0x0290, 0x00000004 }, 273 }; 274 275 static const struct reg_config dbsc_config8[] = { 276 { 0x0304, 0x00000000 }, 277 { 0x00f4, 0x01004c20 }, 278 { 0x00f8, 0x014000aa }, 279 { 0x00e0, 0x00000140 }, 280 { 0x00e4, 0x00081860 }, 281 { 0x00e8, 0x00010000 }, 282 { 0x0014, 0x00000001 }, 283 { 0x0010, 0x00000001 }, 284 { 0x0280, 0x00000000 }, 285 }; 286 287 static const u32 dbsc3_0_base = DBSC3_0_BASE; 288 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; 289 unsigned int i; 290 291 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { 292 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); 293 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); 294 } 295 296 dbsc_wait(0x240); 297 298 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { 299 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); 300 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); 301 } 302 303 dbsc_wait(0x2a0); 304 305 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { 306 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); 307 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); 308 } 309 310 dbsc_wait(0x2a0); 311 312 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { 313 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); 314 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); 315 } 316 317 dbsc_wait(0x2a0); 318 319 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { 320 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); 321 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); 322 } 323 324 } 325 326 static void spl_init_qspi(void) 327 { 328 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 329 330 static const u32 qspi_base = 0xe6b10000; 331 332 writeb(0x08, qspi_base + 0x00); 333 writeb(0x00, qspi_base + 0x01); 334 writeb(0x06, qspi_base + 0x02); 335 writeb(0x01, qspi_base + 0x0a); 336 writeb(0x00, qspi_base + 0x0b); 337 writeb(0x00, qspi_base + 0x0c); 338 writeb(0x00, qspi_base + 0x0d); 339 writeb(0x00, qspi_base + 0x0e); 340 341 writew(0xe080, qspi_base + 0x10); 342 343 writeb(0xc0, qspi_base + 0x18); 344 writeb(0x00, qspi_base + 0x18); 345 writeb(0x00, qspi_base + 0x08); 346 writeb(0x48, qspi_base + 0x00); 347 } 348 349 void board_init_f(ulong dummy) 350 { 351 int i; 352 353 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 354 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 355 356 /* 357 * SD0 clock is set to 97.5MHz by default. 358 * Set SD2 to the 97.5MHz as well. 359 */ 360 writel(SD_97500KHZ, SD2CKCR); 361 362 spl_init_sys(); 363 spl_init_pfc(); 364 spl_init_gpio(); 365 spl_init_lbsc(); 366 367 /* Unknown, likely ES1.0-specific delay */ 368 for (i = 0; i < 100000; i++) 369 asm volatile("nop"); 370 371 spl_init_dbsc(); 372 spl_init_qspi(); 373 } 374 375 void spl_board_init(void) 376 { 377 /* UART clocks enabled and gd valid - init serial console */ 378 preloader_console_init(); 379 } 380 381 void board_boot_order(u32 *spl_boot_list) 382 { 383 const u32 jtag_magic = 0x1337c0de; 384 const u32 load_magic = 0xb33fc0de; 385 386 /* 387 * If JTAG probe sets special word at 0xe6300020, then it must 388 * put U-Boot into RAM and SPL will start it from RAM. 389 */ 390 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { 391 printf("JTAG boot detected!\n"); 392 393 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) 394 ; 395 396 spl_boot_list[0] = BOOT_DEVICE_RAM; 397 spl_boot_list[1] = BOOT_DEVICE_NONE; 398 399 return; 400 } 401 402 /* Boot from SPI NOR with YMODEM UART fallback. */ 403 spl_boot_list[0] = BOOT_DEVICE_SPI; 404 spl_boot_list[1] = BOOT_DEVICE_UART; 405 spl_boot_list[2] = BOOT_DEVICE_NONE; 406 } 407 408 void reset_cpu(ulong addr) 409 { 410 } 411