1 /* 2 * board/renesas/koelsch/koelsch.c 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 * 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <dm.h> 13 #include <dm/platform_data/serial_sh.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/sh_sdhi.h> 23 #include <netdev.h> 24 #include <miiphy.h> 25 #include <i2c.h> 26 #include <div64.h> 27 #include "qos.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define CLK2MHZ(clk) (clk / 1000 / 1000) 32 void s_init(void) 33 { 34 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 35 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 36 u32 stc; 37 38 /* Watchdog init */ 39 writel(0xA5A5A500, &rwdt->rwtcsra); 40 writel(0xA5A5A500, &swdt->swtcsra); 41 42 /* CPU frequency setting. Set to 1.5GHz */ 43 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 44 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 45 46 /* QoS */ 47 qos_init(); 48 } 49 50 #define TMU0_MSTP125 (1 << 25) 51 #define SCIF0_MSTP721 (1 << 21) 52 #define ETHER_MSTP813 (1 << 13) 53 54 #define SDHI0_MSTP314 (1 << 14) 55 #define SDHI1_MSTP312 (1 << 12) 56 #define SDHI2_MSTP311 (1 << 11) 57 58 #define SD1CKCR 0xE6150078 59 #define SD2CKCR 0xE615026C 60 #define SD_97500KHZ 0x7 61 62 int board_early_init_f(void) 63 { 64 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 65 66 /* SCIF0 */ 67 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 68 69 /* ETHER */ 70 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 71 72 /* SDHI */ 73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, 74 SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); 75 76 /* 77 * SD0 clock is set to 97.5MHz by default. 78 * Set SD1 and SD2 to the 97.5MHz as well. 79 */ 80 writel(SD_97500KHZ, SD1CKCR); 81 writel(SD_97500KHZ, SD2CKCR); 82 83 return 0; 84 } 85 86 /* LSI pin pull-up control */ 87 #define PUPR5 0xe6060114 88 #define PUPR5_ETH 0x3FFC0000 89 #define PUPR5_ETH_MAGIC (1 << 27) 90 int board_init(void) 91 { 92 /* adress of boot parameters */ 93 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 94 95 /* Init PFC controller */ 96 r8a7791_pinmux_init(); 97 98 /* ETHER Enable */ 99 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 100 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 101 gpio_request(GPIO_FN_ETH_RXD0, NULL); 102 gpio_request(GPIO_FN_ETH_RXD1, NULL); 103 gpio_request(GPIO_FN_ETH_LINK, NULL); 104 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 105 gpio_request(GPIO_FN_ETH_MDIO, NULL); 106 gpio_request(GPIO_FN_ETH_TXD1, NULL); 107 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 108 gpio_request(GPIO_FN_ETH_TXD0, NULL); 109 gpio_request(GPIO_FN_ETH_MDC, NULL); 110 gpio_request(GPIO_FN_IRQ0, NULL); 111 112 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 113 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 114 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 115 116 gpio_direction_output(GPIO_GP_5_22, 0); 117 mdelay(20); 118 gpio_set_value(GPIO_GP_5_22, 1); 119 udelay(1); 120 121 return 0; 122 } 123 124 #define CXR24 0xEE7003C0 /* MAC address high register */ 125 #define CXR25 0xEE7003C8 /* MAC address low register */ 126 int board_eth_init(bd_t *bis) 127 { 128 #ifdef CONFIG_SH_ETHER 129 int ret = -ENODEV; 130 u32 val; 131 unsigned char enetaddr[6]; 132 133 ret = sh_eth_initialize(bis); 134 if (!eth_env_get_enetaddr("ethaddr", enetaddr)) 135 return ret; 136 137 /* Set Mac address */ 138 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 139 enetaddr[2] << 8 | enetaddr[3]; 140 writel(val, CXR24); 141 142 val = enetaddr[4] << 8 | enetaddr[5]; 143 writel(val, CXR25); 144 145 return ret; 146 #else 147 return 0; 148 #endif 149 } 150 151 int board_mmc_init(bd_t *bis) 152 { 153 int ret = -ENODEV; 154 155 #ifdef CONFIG_SH_SDHI 156 gpio_request(GPIO_FN_SD0_DATA0, NULL); 157 gpio_request(GPIO_FN_SD0_DATA1, NULL); 158 gpio_request(GPIO_FN_SD0_DATA2, NULL); 159 gpio_request(GPIO_FN_SD0_DATA3, NULL); 160 gpio_request(GPIO_FN_SD0_CLK, NULL); 161 gpio_request(GPIO_FN_SD0_CMD, NULL); 162 gpio_request(GPIO_FN_SD0_CD, NULL); 163 gpio_request(GPIO_FN_SD2_DATA0, NULL); 164 gpio_request(GPIO_FN_SD2_DATA1, NULL); 165 gpio_request(GPIO_FN_SD2_DATA2, NULL); 166 gpio_request(GPIO_FN_SD2_DATA3, NULL); 167 gpio_request(GPIO_FN_SD2_CLK, NULL); 168 gpio_request(GPIO_FN_SD2_CMD, NULL); 169 gpio_request(GPIO_FN_SD2_CD, NULL); 170 171 /* SDHI 0 */ 172 gpio_request(GPIO_GP_7_17, NULL); 173 gpio_request(GPIO_GP_2_12, NULL); 174 gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ 175 gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ 176 177 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 178 SH_SDHI_QUIRK_16BIT_BUF); 179 if (ret) 180 return ret; 181 182 /* SDHI 1 */ 183 gpio_request(GPIO_GP_7_18, NULL); 184 gpio_request(GPIO_GP_2_13, NULL); 185 gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ 186 gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ 187 188 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); 189 if (ret) 190 return ret; 191 192 /* SDHI 2 */ 193 gpio_request(GPIO_GP_7_19, NULL); 194 gpio_request(GPIO_GP_2_26, NULL); 195 gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ 196 gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ 197 198 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); 199 #endif 200 return ret; 201 } 202 203 int dram_init(void) 204 { 205 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 206 207 return 0; 208 } 209 210 /* koelsch has KSZ8041NL/RNL */ 211 #define PHY_CONTROL1 0x1E 212 #define PHY_LED_MODE 0xC0000 213 #define PHY_LED_MODE_ACK 0x4000 214 int board_phy_config(struct phy_device *phydev) 215 { 216 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 217 ret &= ~PHY_LED_MODE; 218 ret |= PHY_LED_MODE_ACK; 219 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 220 221 return 0; 222 } 223 224 const struct rmobile_sysinfo sysinfo = { 225 CONFIG_ARCH_RMOBILE_BOARD_STRING 226 }; 227 228 void reset_cpu(ulong addr) 229 { 230 u8 val; 231 232 i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 233 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 234 val |= 0x02; 235 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 236 } 237 238 static const struct sh_serial_platdata serial_platdata = { 239 .base = SCIF0_BASE, 240 .type = PORT_SCIF, 241 .clk = 14745600, 242 .clk_mode = EXT_CLK, 243 }; 244 245 U_BOOT_DEVICE(koelsch_serials) = { 246 .name = "serial_sh", 247 .platdata = &serial_platdata, 248 }; 249