1 /* 2 * board/renesas/koelsch/koelsch.c 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 * 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <asm/processor.h> 13 #include <asm/mach-types.h> 14 #include <asm/io.h> 15 #include <asm/errno.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/rmobile.h> 19 #include <netdev.h> 20 #include <miiphy.h> 21 #include <i2c.h> 22 #include <div64.h> 23 #include "qos.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define CLK2MHZ(clk) (clk / 1000 / 1000) 28 void s_init(void) 29 { 30 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 31 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 32 u32 stc; 33 34 /* Watchdog init */ 35 writel(0xA5A5A500, &rwdt->rwtcsra); 36 writel(0xA5A5A500, &swdt->swtcsra); 37 38 /* CPU frequency setting. Set to 1.5GHz */ 39 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 40 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 41 42 /* QoS */ 43 qos_init(); 44 } 45 46 #define MSTPSR1 0xE6150038 47 #define SMSTPCR1 0xE6150134 48 #define TMU0_MSTP125 (1 << 25) 49 50 #define MSTPSR7 0xE61501C4 51 #define SMSTPCR7 0xE615014C 52 #define SCIF0_MSTP721 (1 << 21) 53 54 #define MSTPSR8 0xE61509A0 55 #define SMSTPCR8 0xE6150990 56 #define ETHER_MSTP813 (1 << 13) 57 58 #define mstp_setbits(type, addr, saddr, set) \ 59 out_##type((saddr), in_##type(addr) | (set)) 60 #define mstp_clrbits(type, addr, saddr, clear) \ 61 out_##type((saddr), in_##type(addr) & ~(clear)) 62 #define mstp_setbits_le32(addr, saddr, set) \ 63 mstp_setbits(le32, addr, saddr, set) 64 #define mstp_clrbits_le32(addr, saddr, clear) \ 65 mstp_clrbits(le32, addr, saddr, clear) 66 67 int board_early_init_f(void) 68 { 69 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 70 71 /* SCIF0 */ 72 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 73 74 /* ETHER */ 75 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 76 77 return 0; 78 } 79 80 void arch_preboot_os(void) 81 { 82 /* Disable TMU0 */ 83 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 84 } 85 86 /* LSI pin pull-up control */ 87 #define PUPR5 0xe6060114 88 #define PUPR5_ETH 0x3FFC0000 89 #define PUPR5_ETH_MAGIC (1 << 27) 90 int board_init(void) 91 { 92 /* adress of boot parameters */ 93 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 94 95 /* Init PFC controller */ 96 r8a7791_pinmux_init(); 97 98 /* ETHER Enable */ 99 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 100 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 101 gpio_request(GPIO_FN_ETH_RXD0, NULL); 102 gpio_request(GPIO_FN_ETH_RXD1, NULL); 103 gpio_request(GPIO_FN_ETH_LINK, NULL); 104 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 105 gpio_request(GPIO_FN_ETH_MDIO, NULL); 106 gpio_request(GPIO_FN_ETH_TXD1, NULL); 107 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 108 gpio_request(GPIO_FN_ETH_TXD0, NULL); 109 gpio_request(GPIO_FN_ETH_MDC, NULL); 110 gpio_request(GPIO_FN_IRQ0, NULL); 111 112 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 113 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 114 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 115 116 gpio_direction_output(GPIO_GP_5_22, 0); 117 mdelay(20); 118 gpio_set_value(GPIO_GP_5_22, 1); 119 udelay(1); 120 121 return 0; 122 } 123 124 #define CXR24 0xEE7003C0 /* MAC address high register */ 125 #define CXR25 0xEE7003C8 /* MAC address low register */ 126 int board_eth_init(bd_t *bis) 127 { 128 #ifdef CONFIG_SH_ETHER 129 int ret = -ENODEV; 130 u32 val; 131 unsigned char enetaddr[6]; 132 133 ret = sh_eth_initialize(bis); 134 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 135 return ret; 136 137 /* Set Mac address */ 138 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 139 enetaddr[2] << 8 | enetaddr[3]; 140 writel(val, CXR24); 141 142 val = enetaddr[4] << 8 | enetaddr[5]; 143 writel(val, CXR25); 144 145 return ret; 146 #else 147 return 0; 148 #endif 149 } 150 151 int dram_init(void) 152 { 153 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 154 155 return 0; 156 } 157 158 /* koelsch has KSZ8041NL/RNL */ 159 #define PHY_CONTROL1 0x1E 160 #define PHY_LED_MODE 0xC0000 161 #define PHY_LED_MODE_ACK 0x4000 162 int board_phy_config(struct phy_device *phydev) 163 { 164 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 165 ret &= ~PHY_LED_MODE; 166 ret |= PHY_LED_MODE_ACK; 167 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 168 169 return 0; 170 } 171 172 const struct rmobile_sysinfo sysinfo = { 173 CONFIG_RMOBILE_BOARD_STRING 174 }; 175 176 void reset_cpu(ulong addr) 177 { 178 u8 val; 179 180 i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 181 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 182 val |= 0x02; 183 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 184 } 185