1 /* 2 * board/renesas/koelsch/koelsch.c 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 * 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <asm/processor.h> 13 #include <asm/mach-types.h> 14 #include <asm/io.h> 15 #include <asm/errno.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/rmobile.h> 19 #include <asm/arch/rcar-mstp.h> 20 #include <netdev.h> 21 #include <miiphy.h> 22 #include <i2c.h> 23 #include <div64.h> 24 #include "qos.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define CLK2MHZ(clk) (clk / 1000 / 1000) 29 void s_init(void) 30 { 31 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 32 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 33 u32 stc; 34 35 /* Watchdog init */ 36 writel(0xA5A5A500, &rwdt->rwtcsra); 37 writel(0xA5A5A500, &swdt->swtcsra); 38 39 /* CPU frequency setting. Set to 1.5GHz */ 40 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 41 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 42 43 /* QoS */ 44 qos_init(); 45 } 46 47 #define TMU0_MSTP125 (1 << 25) 48 #define SCIF0_MSTP721 (1 << 21) 49 #define ETHER_MSTP813 (1 << 13) 50 51 int board_early_init_f(void) 52 { 53 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 54 55 /* SCIF0 */ 56 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 57 58 /* ETHER */ 59 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 60 61 return 0; 62 } 63 64 /* LSI pin pull-up control */ 65 #define PUPR5 0xe6060114 66 #define PUPR5_ETH 0x3FFC0000 67 #define PUPR5_ETH_MAGIC (1 << 27) 68 int board_init(void) 69 { 70 /* adress of boot parameters */ 71 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 72 73 /* Init PFC controller */ 74 r8a7791_pinmux_init(); 75 76 /* ETHER Enable */ 77 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 78 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 79 gpio_request(GPIO_FN_ETH_RXD0, NULL); 80 gpio_request(GPIO_FN_ETH_RXD1, NULL); 81 gpio_request(GPIO_FN_ETH_LINK, NULL); 82 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 83 gpio_request(GPIO_FN_ETH_MDIO, NULL); 84 gpio_request(GPIO_FN_ETH_TXD1, NULL); 85 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 86 gpio_request(GPIO_FN_ETH_TXD0, NULL); 87 gpio_request(GPIO_FN_ETH_MDC, NULL); 88 gpio_request(GPIO_FN_IRQ0, NULL); 89 90 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 91 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 92 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 93 94 gpio_direction_output(GPIO_GP_5_22, 0); 95 mdelay(20); 96 gpio_set_value(GPIO_GP_5_22, 1); 97 udelay(1); 98 99 return 0; 100 } 101 102 #define CXR24 0xEE7003C0 /* MAC address high register */ 103 #define CXR25 0xEE7003C8 /* MAC address low register */ 104 int board_eth_init(bd_t *bis) 105 { 106 #ifdef CONFIG_SH_ETHER 107 int ret = -ENODEV; 108 u32 val; 109 unsigned char enetaddr[6]; 110 111 ret = sh_eth_initialize(bis); 112 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 113 return ret; 114 115 /* Set Mac address */ 116 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 117 enetaddr[2] << 8 | enetaddr[3]; 118 writel(val, CXR24); 119 120 val = enetaddr[4] << 8 | enetaddr[5]; 121 writel(val, CXR25); 122 123 return ret; 124 #else 125 return 0; 126 #endif 127 } 128 129 int dram_init(void) 130 { 131 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 132 133 return 0; 134 } 135 136 /* koelsch has KSZ8041NL/RNL */ 137 #define PHY_CONTROL1 0x1E 138 #define PHY_LED_MODE 0xC0000 139 #define PHY_LED_MODE_ACK 0x4000 140 int board_phy_config(struct phy_device *phydev) 141 { 142 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 143 ret &= ~PHY_LED_MODE; 144 ret |= PHY_LED_MODE_ACK; 145 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 146 147 return 0; 148 } 149 150 const struct rmobile_sysinfo sysinfo = { 151 CONFIG_RMOBILE_BOARD_STRING 152 }; 153 154 void reset_cpu(ulong addr) 155 { 156 u8 val; 157 158 i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 159 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 160 val |= 0x02; 161 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 162 } 163