11251e490SNobuhiro Iwamatsu /* 21251e490SNobuhiro Iwamatsu * board/renesas/koelsch/koelsch.c 31251e490SNobuhiro Iwamatsu * 41251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 51251e490SNobuhiro Iwamatsu * 61251e490SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 71251e490SNobuhiro Iwamatsu * 81251e490SNobuhiro Iwamatsu */ 91251e490SNobuhiro Iwamatsu 101251e490SNobuhiro Iwamatsu #include <common.h> 111251e490SNobuhiro Iwamatsu #include <malloc.h> 121251e490SNobuhiro Iwamatsu #include <asm/processor.h> 131251e490SNobuhiro Iwamatsu #include <asm/mach-types.h> 141251e490SNobuhiro Iwamatsu #include <asm/io.h> 151251e490SNobuhiro Iwamatsu #include <asm/errno.h> 161251e490SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 171251e490SNobuhiro Iwamatsu #include <asm/gpio.h> 181251e490SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 1990362c0cSNobuhiro Iwamatsu #include <netdev.h> 2090362c0cSNobuhiro Iwamatsu #include <miiphy.h> 211251e490SNobuhiro Iwamatsu #include <i2c.h> 221251e490SNobuhiro Iwamatsu #include "qos.h" 231251e490SNobuhiro Iwamatsu 241251e490SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 251251e490SNobuhiro Iwamatsu 261251e490SNobuhiro Iwamatsu #define s_init_wait(cnt) \ 271251e490SNobuhiro Iwamatsu ({ \ 281251e490SNobuhiro Iwamatsu u32 i = 0x10000 * cnt; \ 291251e490SNobuhiro Iwamatsu while (i > 0) \ 301251e490SNobuhiro Iwamatsu i--; \ 311251e490SNobuhiro Iwamatsu }) 321251e490SNobuhiro Iwamatsu 331251e490SNobuhiro Iwamatsu 341251e490SNobuhiro Iwamatsu #define dbpdrgd_check(bsc) \ 351251e490SNobuhiro Iwamatsu ({ \ 361251e490SNobuhiro Iwamatsu while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \ 371251e490SNobuhiro Iwamatsu ; \ 381251e490SNobuhiro Iwamatsu }) 391251e490SNobuhiro Iwamatsu 401251e490SNobuhiro Iwamatsu #if defined(CONFIG_NORFLASH) 411251e490SNobuhiro Iwamatsu static void bsc_init(void) 421251e490SNobuhiro Iwamatsu { 431251e490SNobuhiro Iwamatsu struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE; 441251e490SNobuhiro Iwamatsu struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE; 451251e490SNobuhiro Iwamatsu 461251e490SNobuhiro Iwamatsu /* LBSC */ 471251e490SNobuhiro Iwamatsu writel(0x00000020, &lbsc->cs0ctrl); 481251e490SNobuhiro Iwamatsu writel(0x00000020, &lbsc->cs1ctrl); 491251e490SNobuhiro Iwamatsu writel(0x00002020, &lbsc->ecs0ctrl); 501251e490SNobuhiro Iwamatsu writel(0x00002020, &lbsc->ecs1ctrl); 511251e490SNobuhiro Iwamatsu 521251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->cswcr0); 531251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->cswcr1); 541251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->ecswcr0); 551251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->ecswcr1); 561251e490SNobuhiro Iwamatsu 571251e490SNobuhiro Iwamatsu /* DBSC3 */ 581251e490SNobuhiro Iwamatsu s_init_wait(10); 591251e490SNobuhiro Iwamatsu 601251e490SNobuhiro Iwamatsu writel(0x0000A55A, &dbsc3_0->dbpdlck); 611251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 621251e490SNobuhiro Iwamatsu writel(0x80000000, &dbsc3_0->dbpdrgd); 631251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 641251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 651251e490SNobuhiro Iwamatsu 661251e490SNobuhiro Iwamatsu writel(0x00000006, &dbsc3_0->dbpdrga); 671251e490SNobuhiro Iwamatsu writel(0x0001C000, &dbsc3_0->dbpdrgd); 681251e490SNobuhiro Iwamatsu 691251e490SNobuhiro Iwamatsu writel(0x00000023, &dbsc3_0->dbpdrga); 701251e490SNobuhiro Iwamatsu writel(0x00FD2480, &dbsc3_0->dbpdrgd); 711251e490SNobuhiro Iwamatsu 721251e490SNobuhiro Iwamatsu writel(0x00000010, &dbsc3_0->dbpdrga); 731251e490SNobuhiro Iwamatsu writel(0xF004649B, &dbsc3_0->dbpdrgd); 741251e490SNobuhiro Iwamatsu 751251e490SNobuhiro Iwamatsu writel(0x0000000F, &dbsc3_0->dbpdrga); 761251e490SNobuhiro Iwamatsu writel(0x00181EE4, &dbsc3_0->dbpdrgd); 771251e490SNobuhiro Iwamatsu 781251e490SNobuhiro Iwamatsu writel(0x0000000E, &dbsc3_0->dbpdrga); 791251e490SNobuhiro Iwamatsu writel(0x33C03812, &dbsc3_0->dbpdrgd); 801251e490SNobuhiro Iwamatsu 811251e490SNobuhiro Iwamatsu writel(0x00000003, &dbsc3_0->dbpdrga); 821251e490SNobuhiro Iwamatsu writel(0x0300C481, &dbsc3_0->dbpdrgd); 831251e490SNobuhiro Iwamatsu 841251e490SNobuhiro Iwamatsu writel(0x00000007, &dbsc3_0->dbkind); 851251e490SNobuhiro Iwamatsu writel(0x10030A02, &dbsc3_0->dbconf0); 861251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbphytype); 871251e490SNobuhiro Iwamatsu writel(0x00000000, &dbsc3_0->dbbl); 881251e490SNobuhiro Iwamatsu writel(0x0000000B, &dbsc3_0->dbtr0); 891251e490SNobuhiro Iwamatsu writel(0x00000008, &dbsc3_0->dbtr1); 901251e490SNobuhiro Iwamatsu writel(0x00000000, &dbsc3_0->dbtr2); 911251e490SNobuhiro Iwamatsu writel(0x0000000B, &dbsc3_0->dbtr3); 921251e490SNobuhiro Iwamatsu writel(0x000C000B, &dbsc3_0->dbtr4); 931251e490SNobuhiro Iwamatsu writel(0x00000027, &dbsc3_0->dbtr5); 941251e490SNobuhiro Iwamatsu writel(0x0000001C, &dbsc3_0->dbtr6); 951251e490SNobuhiro Iwamatsu writel(0x00000005, &dbsc3_0->dbtr7); 961251e490SNobuhiro Iwamatsu writel(0x00000018, &dbsc3_0->dbtr8); 971251e490SNobuhiro Iwamatsu writel(0x00000008, &dbsc3_0->dbtr9); 981251e490SNobuhiro Iwamatsu writel(0x0000000C, &dbsc3_0->dbtr10); 991251e490SNobuhiro Iwamatsu writel(0x00000009, &dbsc3_0->dbtr11); 1001251e490SNobuhiro Iwamatsu writel(0x00000012, &dbsc3_0->dbtr12); 1011251e490SNobuhiro Iwamatsu writel(0x000000D0, &dbsc3_0->dbtr13); 1021251e490SNobuhiro Iwamatsu writel(0x00140005, &dbsc3_0->dbtr14); 1031251e490SNobuhiro Iwamatsu writel(0x00050004, &dbsc3_0->dbtr15); 1041251e490SNobuhiro Iwamatsu writel(0x70233005, &dbsc3_0->dbtr16); 1051251e490SNobuhiro Iwamatsu writel(0x000C0000, &dbsc3_0->dbtr17); 1061251e490SNobuhiro Iwamatsu writel(0x00000300, &dbsc3_0->dbtr18); 1071251e490SNobuhiro Iwamatsu writel(0x00000040, &dbsc3_0->dbtr19); 1081251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbrnk0); 1091251e490SNobuhiro Iwamatsu writel(0x00020001, &dbsc3_0->dbadj0); 1101251e490SNobuhiro Iwamatsu writel(0x20082008, &dbsc3_0->dbadj2); 1111251e490SNobuhiro Iwamatsu writel(0x00020002, &dbsc3_0->dbwt0cnf0); 1121251e490SNobuhiro Iwamatsu writel(0x0000000F, &dbsc3_0->dbwt0cnf4); 1131251e490SNobuhiro Iwamatsu 1141251e490SNobuhiro Iwamatsu writel(0x00000015, &dbsc3_0->dbpdrga); 1151251e490SNobuhiro Iwamatsu writel(0x00000D70, &dbsc3_0->dbpdrgd); 1161251e490SNobuhiro Iwamatsu 1171251e490SNobuhiro Iwamatsu writel(0x00000016, &dbsc3_0->dbpdrga); 1181251e490SNobuhiro Iwamatsu writel(0x00000006, &dbsc3_0->dbpdrgd); 1191251e490SNobuhiro Iwamatsu 1201251e490SNobuhiro Iwamatsu writel(0x00000017, &dbsc3_0->dbpdrga); 1211251e490SNobuhiro Iwamatsu writel(0x00000018, &dbsc3_0->dbpdrgd); 1221251e490SNobuhiro Iwamatsu 1231251e490SNobuhiro Iwamatsu writel(0x00000012, &dbsc3_0->dbpdrga); 1241251e490SNobuhiro Iwamatsu writel(0x9D5CBB66, &dbsc3_0->dbpdrgd); 1251251e490SNobuhiro Iwamatsu 1261251e490SNobuhiro Iwamatsu writel(0x00000013, &dbsc3_0->dbpdrga); 1271251e490SNobuhiro Iwamatsu writel(0x1A868300, &dbsc3_0->dbpdrgd); 1281251e490SNobuhiro Iwamatsu 1291251e490SNobuhiro Iwamatsu writel(0x00000023, &dbsc3_0->dbpdrga); 1301251e490SNobuhiro Iwamatsu writel(0x00FDB6C0, &dbsc3_0->dbpdrgd); 1311251e490SNobuhiro Iwamatsu 1321251e490SNobuhiro Iwamatsu writel(0x00000014, &dbsc3_0->dbpdrga); 1331251e490SNobuhiro Iwamatsu writel(0x300214D8, &dbsc3_0->dbpdrgd); 1341251e490SNobuhiro Iwamatsu 1351251e490SNobuhiro Iwamatsu writel(0x0000001A, &dbsc3_0->dbpdrga); 1361251e490SNobuhiro Iwamatsu writel(0x930035C7, &dbsc3_0->dbpdrgd); 1371251e490SNobuhiro Iwamatsu 1381251e490SNobuhiro Iwamatsu writel(0x00000060, &dbsc3_0->dbpdrga); 1391251e490SNobuhiro Iwamatsu writel(0x330657B2, &dbsc3_0->dbpdrgd); 1401251e490SNobuhiro Iwamatsu 1411251e490SNobuhiro Iwamatsu writel(0x00000011, &dbsc3_0->dbpdrga); 1421251e490SNobuhiro Iwamatsu writel(0x1000040B, &dbsc3_0->dbpdrgd); 1431251e490SNobuhiro Iwamatsu 1441251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1451251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 1461251e490SNobuhiro Iwamatsu writel(0x00000071, &dbsc3_0->dbpdrgd); 1471251e490SNobuhiro Iwamatsu 1481251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 1491251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 1501251e490SNobuhiro Iwamatsu 1511251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1521251e490SNobuhiro Iwamatsu writel(0x2100FA00, &dbsc3_0->dbcmd); 1531251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1541251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1551251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1561251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1571251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1581251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1591251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 1601251e490SNobuhiro Iwamatsu 1611251e490SNobuhiro Iwamatsu writel(0x110000DB, &dbsc3_0->dbcmd); 1621251e490SNobuhiro Iwamatsu 1631251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 1641251e490SNobuhiro Iwamatsu writel(0x00000181, &dbsc3_0->dbpdrgd); 1651251e490SNobuhiro Iwamatsu 1661251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 1671251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 1681251e490SNobuhiro Iwamatsu 1691251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 1701251e490SNobuhiro Iwamatsu writel(0x0000FE01, &dbsc3_0->dbpdrgd); 1711251e490SNobuhiro Iwamatsu 1721251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 1731251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 1741251e490SNobuhiro Iwamatsu 1751251e490SNobuhiro Iwamatsu writel(0x00000000, &dbsc3_0->dbbs0cnt1); 1761251e490SNobuhiro Iwamatsu writel(0x01004C20, &dbsc3_0->dbcalcnf); 1771251e490SNobuhiro Iwamatsu writel(0x014000AA, &dbsc3_0->dbcaltr); 1781251e490SNobuhiro Iwamatsu writel(0x00000140, &dbsc3_0->dbrfcnf0); 1791251e490SNobuhiro Iwamatsu writel(0x00081860, &dbsc3_0->dbrfcnf1); 1801251e490SNobuhiro Iwamatsu writel(0x00010000, &dbsc3_0->dbrfcnf2); 1811251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbrfen); 1821251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbacen); 1831251e490SNobuhiro Iwamatsu } 1841251e490SNobuhiro Iwamatsu #else 1851251e490SNobuhiro Iwamatsu #define bsc_init() do {} while (0) 1861251e490SNobuhiro Iwamatsu #endif /* CONFIG_NORFLASH */ 1871251e490SNobuhiro Iwamatsu 1881251e490SNobuhiro Iwamatsu void s_init(void) 1891251e490SNobuhiro Iwamatsu { 1901251e490SNobuhiro Iwamatsu struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE; 1911251e490SNobuhiro Iwamatsu struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE; 1921251e490SNobuhiro Iwamatsu 1931251e490SNobuhiro Iwamatsu /* Watchdog init */ 1941251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 1951251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 1961251e490SNobuhiro Iwamatsu 1971251e490SNobuhiro Iwamatsu /* QoS */ 1981251e490SNobuhiro Iwamatsu qos_init(); 1991251e490SNobuhiro Iwamatsu 2001251e490SNobuhiro Iwamatsu /* BSC */ 2011251e490SNobuhiro Iwamatsu bsc_init(); 2021251e490SNobuhiro Iwamatsu } 2031251e490SNobuhiro Iwamatsu 2041251e490SNobuhiro Iwamatsu #define MSTPSR1 0xE6150038 2051251e490SNobuhiro Iwamatsu #define SMSTPCR1 0xE6150134 2061251e490SNobuhiro Iwamatsu #define TMU0_MSTP125 (1 << 25) 2071251e490SNobuhiro Iwamatsu 2081251e490SNobuhiro Iwamatsu #define MSTPSR7 0xE61501C4 2091251e490SNobuhiro Iwamatsu #define SMSTPCR7 0xE615014C 2101251e490SNobuhiro Iwamatsu #define SCIF0_MSTP721 (1 << 21) 2111251e490SNobuhiro Iwamatsu 21290362c0cSNobuhiro Iwamatsu #define MSTPSR8 0xE61509A0 21390362c0cSNobuhiro Iwamatsu #define SMSTPCR8 0xE6150990 21490362c0cSNobuhiro Iwamatsu #define ETHER_MSTP813 (1 << 13) 21590362c0cSNobuhiro Iwamatsu 2161251e490SNobuhiro Iwamatsu #define PMMR 0xE6060000 2171251e490SNobuhiro Iwamatsu #define GPSR4 0xE6060014 2181251e490SNobuhiro Iwamatsu #define IPSR14 0xE6060058 2191251e490SNobuhiro Iwamatsu 2201251e490SNobuhiro Iwamatsu #define set_guard_reg(addr, mask, value) \ 2211251e490SNobuhiro Iwamatsu { \ 2221251e490SNobuhiro Iwamatsu u32 val; \ 2231251e490SNobuhiro Iwamatsu val = (readl(addr) & ~(mask)) | (value); \ 2241251e490SNobuhiro Iwamatsu writel(~val, PMMR); \ 2251251e490SNobuhiro Iwamatsu writel(val, addr); \ 2261251e490SNobuhiro Iwamatsu } 2271251e490SNobuhiro Iwamatsu 2281251e490SNobuhiro Iwamatsu #define mstp_setbits(type, addr, saddr, set) \ 2291251e490SNobuhiro Iwamatsu out_##type((saddr), in_##type(addr) | (set)) 2301251e490SNobuhiro Iwamatsu #define mstp_clrbits(type, addr, saddr, clear) \ 2311251e490SNobuhiro Iwamatsu out_##type((saddr), in_##type(addr) & ~(clear)) 2321251e490SNobuhiro Iwamatsu #define mstp_setbits_le32(addr, saddr, set) \ 2331251e490SNobuhiro Iwamatsu mstp_setbits(le32, addr, saddr, set) 2341251e490SNobuhiro Iwamatsu #define mstp_clrbits_le32(addr, saddr, clear) \ 2351251e490SNobuhiro Iwamatsu mstp_clrbits(le32, addr, saddr, clear) 2361251e490SNobuhiro Iwamatsu 2371251e490SNobuhiro Iwamatsu int board_early_init_f(void) 2381251e490SNobuhiro Iwamatsu { 2391251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 2401251e490SNobuhiro Iwamatsu 2411251e490SNobuhiro Iwamatsu #if defined(CONFIG_NORFLASH) 2421251e490SNobuhiro Iwamatsu /* SCIF0 */ 2431251e490SNobuhiro Iwamatsu set_guard_reg(GPSR4, 0x34000000, 0x00000000); 2441251e490SNobuhiro Iwamatsu set_guard_reg(IPSR14, 0x00000FC7, 0x00000481); 2451251e490SNobuhiro Iwamatsu set_guard_reg(GPSR4, 0x00000000, 0x34000000); 2461251e490SNobuhiro Iwamatsu #endif 2471251e490SNobuhiro Iwamatsu 2481251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 2491251e490SNobuhiro Iwamatsu 25090362c0cSNobuhiro Iwamatsu /* ETHER */ 25190362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 25290362c0cSNobuhiro Iwamatsu 2531251e490SNobuhiro Iwamatsu return 0; 2541251e490SNobuhiro Iwamatsu } 2551251e490SNobuhiro Iwamatsu 25690362c0cSNobuhiro Iwamatsu /* LSI pin pull-up control */ 25790362c0cSNobuhiro Iwamatsu #define PUPR5 0xe6060114 25890362c0cSNobuhiro Iwamatsu #define PUPR5_ETH 0x3FFC0000 25990362c0cSNobuhiro Iwamatsu #define PUPR5_ETH_MAGIC (1 << 27) 2601251e490SNobuhiro Iwamatsu int board_init(void) 2611251e490SNobuhiro Iwamatsu { 2621251e490SNobuhiro Iwamatsu /* adress of boot parameters */ 2631251e490SNobuhiro Iwamatsu gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100; 2641251e490SNobuhiro Iwamatsu 2651251e490SNobuhiro Iwamatsu /* Init PFC controller */ 2661251e490SNobuhiro Iwamatsu r8a7791_pinmux_init(); 2671251e490SNobuhiro Iwamatsu 26890362c0cSNobuhiro Iwamatsu /* ETHER Enable */ 26990362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 27090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RX_ER, NULL); 27190362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD0, NULL); 27290362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD1, NULL); 27390362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_LINK, NULL); 27490362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_REFCLK, NULL); 27590362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDIO, NULL); 27690362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD1, NULL); 27790362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TX_EN, NULL); 27890362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD0, NULL); 27990362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDC, NULL); 28090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_IRQ0, NULL); 28190362c0cSNobuhiro Iwamatsu 28290362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 28390362c0cSNobuhiro Iwamatsu gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 28490362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 28590362c0cSNobuhiro Iwamatsu 28690362c0cSNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_5_22, 0); 28790362c0cSNobuhiro Iwamatsu mdelay(20); 28890362c0cSNobuhiro Iwamatsu gpio_set_value(GPIO_GP_5_22, 1); 28990362c0cSNobuhiro Iwamatsu udelay(1); 29090362c0cSNobuhiro Iwamatsu 2911251e490SNobuhiro Iwamatsu return 0; 2921251e490SNobuhiro Iwamatsu } 2931251e490SNobuhiro Iwamatsu 29490362c0cSNobuhiro Iwamatsu #define CXR24 0xEE7003C0 /* MAC address high register */ 29590362c0cSNobuhiro Iwamatsu #define CXR25 0xEE7003C8 /* MAC address low register */ 29690362c0cSNobuhiro Iwamatsu int board_eth_init(bd_t *bis) 29790362c0cSNobuhiro Iwamatsu { 29890362c0cSNobuhiro Iwamatsu #ifdef CONFIG_SH_ETHER 29990362c0cSNobuhiro Iwamatsu int ret = -ENODEV; 30090362c0cSNobuhiro Iwamatsu u32 val; 30190362c0cSNobuhiro Iwamatsu unsigned char enetaddr[6]; 30290362c0cSNobuhiro Iwamatsu 30390362c0cSNobuhiro Iwamatsu ret = sh_eth_initialize(bis); 30490362c0cSNobuhiro Iwamatsu if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 30590362c0cSNobuhiro Iwamatsu return ret; 30690362c0cSNobuhiro Iwamatsu 30790362c0cSNobuhiro Iwamatsu /* Set Mac address */ 30890362c0cSNobuhiro Iwamatsu val = enetaddr[0] << 24 | enetaddr[1] << 16 | 30990362c0cSNobuhiro Iwamatsu enetaddr[2] << 8 | enetaddr[3]; 31090362c0cSNobuhiro Iwamatsu writel(val, CXR24); 31190362c0cSNobuhiro Iwamatsu 31290362c0cSNobuhiro Iwamatsu val = enetaddr[4] << 8 | enetaddr[5]; 31390362c0cSNobuhiro Iwamatsu writel(val, CXR25); 31490362c0cSNobuhiro Iwamatsu 31590362c0cSNobuhiro Iwamatsu return ret; 31690362c0cSNobuhiro Iwamatsu #else 31790362c0cSNobuhiro Iwamatsu return 0; 31890362c0cSNobuhiro Iwamatsu #endif 31990362c0cSNobuhiro Iwamatsu } 32090362c0cSNobuhiro Iwamatsu 3211251e490SNobuhiro Iwamatsu int dram_init(void) 3221251e490SNobuhiro Iwamatsu { 3231251e490SNobuhiro Iwamatsu gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 3241251e490SNobuhiro Iwamatsu gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 3251251e490SNobuhiro Iwamatsu 3261251e490SNobuhiro Iwamatsu return 0; 3271251e490SNobuhiro Iwamatsu } 3281251e490SNobuhiro Iwamatsu 32990362c0cSNobuhiro Iwamatsu /* koelsch has KSZ8041NL/RNL */ 33090362c0cSNobuhiro Iwamatsu #define PHY_CONTROL1 0x1E 33190362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE 0xC0000 33290362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE_ACK 0x4000 33390362c0cSNobuhiro Iwamatsu int board_phy_config(struct phy_device *phydev) 33490362c0cSNobuhiro Iwamatsu { 33590362c0cSNobuhiro Iwamatsu int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 33690362c0cSNobuhiro Iwamatsu ret &= ~PHY_LED_MODE; 33790362c0cSNobuhiro Iwamatsu ret |= PHY_LED_MODE_ACK; 33890362c0cSNobuhiro Iwamatsu ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 33990362c0cSNobuhiro Iwamatsu 34090362c0cSNobuhiro Iwamatsu return 0; 34190362c0cSNobuhiro Iwamatsu } 34290362c0cSNobuhiro Iwamatsu 3431251e490SNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 3441251e490SNobuhiro Iwamatsu CONFIG_RMOBILE_BOARD_STRING 3451251e490SNobuhiro Iwamatsu }; 3461251e490SNobuhiro Iwamatsu 3471251e490SNobuhiro Iwamatsu void dram_init_banksize(void) 3481251e490SNobuhiro Iwamatsu { 3491251e490SNobuhiro Iwamatsu gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE; 3501251e490SNobuhiro Iwamatsu gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE; 3511251e490SNobuhiro Iwamatsu } 3521251e490SNobuhiro Iwamatsu 3531251e490SNobuhiro Iwamatsu int board_late_init(void) 3541251e490SNobuhiro Iwamatsu { 3551251e490SNobuhiro Iwamatsu return 0; 3561251e490SNobuhiro Iwamatsu } 3571251e490SNobuhiro Iwamatsu 3581251e490SNobuhiro Iwamatsu void reset_cpu(ulong addr) 3591251e490SNobuhiro Iwamatsu { 360*b8f383b8SNobuhiro Iwamatsu u8 val; 361*b8f383b8SNobuhiro Iwamatsu 362*b8f383b8SNobuhiro Iwamatsu i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 363*b8f383b8SNobuhiro Iwamatsu i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 364*b8f383b8SNobuhiro Iwamatsu val |= 0x02; 365*b8f383b8SNobuhiro Iwamatsu i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 3661251e490SNobuhiro Iwamatsu } 367