11251e490SNobuhiro Iwamatsu /* 21251e490SNobuhiro Iwamatsu * board/renesas/koelsch/koelsch.c 31251e490SNobuhiro Iwamatsu * 41251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 51251e490SNobuhiro Iwamatsu * 61251e490SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 71251e490SNobuhiro Iwamatsu * 81251e490SNobuhiro Iwamatsu */ 91251e490SNobuhiro Iwamatsu 101251e490SNobuhiro Iwamatsu #include <common.h> 111251e490SNobuhiro Iwamatsu #include <malloc.h> 120bf51cb0SNobuhiro Iwamatsu #include <dm.h> 130bf51cb0SNobuhiro Iwamatsu #include <dm/platform_data/serial_sh.h> 14*9925f1dbSAlex Kiernan #include <environment.h> 151251e490SNobuhiro Iwamatsu #include <asm/processor.h> 161251e490SNobuhiro Iwamatsu #include <asm/mach-types.h> 171251e490SNobuhiro Iwamatsu #include <asm/io.h> 181221ce45SMasahiro Yamada #include <linux/errno.h> 191251e490SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 201251e490SNobuhiro Iwamatsu #include <asm/gpio.h> 211251e490SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 2244e1eebfSNobuhiro Iwamatsu #include <asm/arch/rcar-mstp.h> 2311e32910SNobuhiro Iwamatsu #include <asm/arch/sh_sdhi.h> 2490362c0cSNobuhiro Iwamatsu #include <netdev.h> 2590362c0cSNobuhiro Iwamatsu #include <miiphy.h> 261251e490SNobuhiro Iwamatsu #include <i2c.h> 27ccde6771SNobuhiro Iwamatsu #include <div64.h> 281251e490SNobuhiro Iwamatsu #include "qos.h" 291251e490SNobuhiro Iwamatsu 301251e490SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 311251e490SNobuhiro Iwamatsu 32ccde6771SNobuhiro Iwamatsu #define CLK2MHZ(clk) (clk / 1000 / 1000) 331251e490SNobuhiro Iwamatsu void s_init(void) 341251e490SNobuhiro Iwamatsu { 35ec9b386eSNobuhiro Iwamatsu struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 36ec9b386eSNobuhiro Iwamatsu struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 37ccde6771SNobuhiro Iwamatsu u32 stc; 381251e490SNobuhiro Iwamatsu 391251e490SNobuhiro Iwamatsu /* Watchdog init */ 401251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 411251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 421251e490SNobuhiro Iwamatsu 43ccde6771SNobuhiro Iwamatsu /* CPU frequency setting. Set to 1.5GHz */ 44ccde6771SNobuhiro Iwamatsu stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 45ccde6771SNobuhiro Iwamatsu clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 46ccde6771SNobuhiro Iwamatsu 471251e490SNobuhiro Iwamatsu /* QoS */ 481251e490SNobuhiro Iwamatsu qos_init(); 491251e490SNobuhiro Iwamatsu } 501251e490SNobuhiro Iwamatsu 511251e490SNobuhiro Iwamatsu #define TMU0_MSTP125 (1 << 25) 521251e490SNobuhiro Iwamatsu #define SCIF0_MSTP721 (1 << 21) 5390362c0cSNobuhiro Iwamatsu #define ETHER_MSTP813 (1 << 13) 5490362c0cSNobuhiro Iwamatsu 5511e32910SNobuhiro Iwamatsu #define SDHI0_MSTP314 (1 << 14) 5611e32910SNobuhiro Iwamatsu #define SDHI1_MSTP312 (1 << 12) 5711e32910SNobuhiro Iwamatsu #define SDHI2_MSTP311 (1 << 11) 5811e32910SNobuhiro Iwamatsu 5911e32910SNobuhiro Iwamatsu #define SD1CKCR 0xE6150078 6011e32910SNobuhiro Iwamatsu #define SD2CKCR 0xE615026C 6111e32910SNobuhiro Iwamatsu #define SD_97500KHZ 0x7 6211e32910SNobuhiro Iwamatsu 631251e490SNobuhiro Iwamatsu int board_early_init_f(void) 641251e490SNobuhiro Iwamatsu { 651251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 661251e490SNobuhiro Iwamatsu 671251e490SNobuhiro Iwamatsu /* SCIF0 */ 681251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 691251e490SNobuhiro Iwamatsu 7090362c0cSNobuhiro Iwamatsu /* ETHER */ 7190362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 7290362c0cSNobuhiro Iwamatsu 7311e32910SNobuhiro Iwamatsu /* SDHI */ 7411e32910SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR3, SMSTPCR3, 7511e32910SNobuhiro Iwamatsu SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); 7611e32910SNobuhiro Iwamatsu 7711e32910SNobuhiro Iwamatsu /* 7811e32910SNobuhiro Iwamatsu * SD0 clock is set to 97.5MHz by default. 7911e32910SNobuhiro Iwamatsu * Set SD1 and SD2 to the 97.5MHz as well. 8011e32910SNobuhiro Iwamatsu */ 8111e32910SNobuhiro Iwamatsu writel(SD_97500KHZ, SD1CKCR); 8211e32910SNobuhiro Iwamatsu writel(SD_97500KHZ, SD2CKCR); 8311e32910SNobuhiro Iwamatsu 841251e490SNobuhiro Iwamatsu return 0; 851251e490SNobuhiro Iwamatsu } 861251e490SNobuhiro Iwamatsu 8790362c0cSNobuhiro Iwamatsu /* LSI pin pull-up control */ 8890362c0cSNobuhiro Iwamatsu #define PUPR5 0xe6060114 8990362c0cSNobuhiro Iwamatsu #define PUPR5_ETH 0x3FFC0000 9090362c0cSNobuhiro Iwamatsu #define PUPR5_ETH_MAGIC (1 << 27) 911251e490SNobuhiro Iwamatsu int board_init(void) 921251e490SNobuhiro Iwamatsu { 931251e490SNobuhiro Iwamatsu /* adress of boot parameters */ 94956556fbSNobuhiro Iwamatsu gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 951251e490SNobuhiro Iwamatsu 961251e490SNobuhiro Iwamatsu /* Init PFC controller */ 971251e490SNobuhiro Iwamatsu r8a7791_pinmux_init(); 981251e490SNobuhiro Iwamatsu 9990362c0cSNobuhiro Iwamatsu /* ETHER Enable */ 10090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 10190362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RX_ER, NULL); 10290362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD0, NULL); 10390362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD1, NULL); 10490362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_LINK, NULL); 10590362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_REFCLK, NULL); 10690362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDIO, NULL); 10790362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD1, NULL); 10890362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TX_EN, NULL); 10990362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD0, NULL); 11090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDC, NULL); 11190362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_IRQ0, NULL); 11290362c0cSNobuhiro Iwamatsu 11390362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 11490362c0cSNobuhiro Iwamatsu gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 11590362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 11690362c0cSNobuhiro Iwamatsu 11790362c0cSNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_5_22, 0); 11890362c0cSNobuhiro Iwamatsu mdelay(20); 11990362c0cSNobuhiro Iwamatsu gpio_set_value(GPIO_GP_5_22, 1); 12090362c0cSNobuhiro Iwamatsu udelay(1); 12190362c0cSNobuhiro Iwamatsu 1221251e490SNobuhiro Iwamatsu return 0; 1231251e490SNobuhiro Iwamatsu } 1241251e490SNobuhiro Iwamatsu 12590362c0cSNobuhiro Iwamatsu #define CXR24 0xEE7003C0 /* MAC address high register */ 12690362c0cSNobuhiro Iwamatsu #define CXR25 0xEE7003C8 /* MAC address low register */ 12790362c0cSNobuhiro Iwamatsu int board_eth_init(bd_t *bis) 12890362c0cSNobuhiro Iwamatsu { 12990362c0cSNobuhiro Iwamatsu #ifdef CONFIG_SH_ETHER 13090362c0cSNobuhiro Iwamatsu int ret = -ENODEV; 13190362c0cSNobuhiro Iwamatsu u32 val; 13290362c0cSNobuhiro Iwamatsu unsigned char enetaddr[6]; 13390362c0cSNobuhiro Iwamatsu 13490362c0cSNobuhiro Iwamatsu ret = sh_eth_initialize(bis); 13535affd7aSSimon Glass if (!eth_env_get_enetaddr("ethaddr", enetaddr)) 13690362c0cSNobuhiro Iwamatsu return ret; 13790362c0cSNobuhiro Iwamatsu 13890362c0cSNobuhiro Iwamatsu /* Set Mac address */ 13990362c0cSNobuhiro Iwamatsu val = enetaddr[0] << 24 | enetaddr[1] << 16 | 14090362c0cSNobuhiro Iwamatsu enetaddr[2] << 8 | enetaddr[3]; 14190362c0cSNobuhiro Iwamatsu writel(val, CXR24); 14290362c0cSNobuhiro Iwamatsu 14390362c0cSNobuhiro Iwamatsu val = enetaddr[4] << 8 | enetaddr[5]; 14490362c0cSNobuhiro Iwamatsu writel(val, CXR25); 14590362c0cSNobuhiro Iwamatsu 14690362c0cSNobuhiro Iwamatsu return ret; 14790362c0cSNobuhiro Iwamatsu #else 14890362c0cSNobuhiro Iwamatsu return 0; 14990362c0cSNobuhiro Iwamatsu #endif 15090362c0cSNobuhiro Iwamatsu } 15190362c0cSNobuhiro Iwamatsu 15211e32910SNobuhiro Iwamatsu int board_mmc_init(bd_t *bis) 15311e32910SNobuhiro Iwamatsu { 15411e32910SNobuhiro Iwamatsu int ret = -ENODEV; 15511e32910SNobuhiro Iwamatsu 15611e32910SNobuhiro Iwamatsu #ifdef CONFIG_SH_SDHI 15711e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD0_DATA0, NULL); 15811e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD0_DATA1, NULL); 15911e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD0_DATA2, NULL); 16011e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD0_DATA3, NULL); 16111e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD0_CLK, NULL); 16211e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD0_CMD, NULL); 16311e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD0_CD, NULL); 16411e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD2_DATA0, NULL); 16511e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD2_DATA1, NULL); 16611e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD2_DATA2, NULL); 16711e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD2_DATA3, NULL); 16811e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD2_CLK, NULL); 16911e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD2_CMD, NULL); 17011e32910SNobuhiro Iwamatsu gpio_request(GPIO_FN_SD2_CD, NULL); 17111e32910SNobuhiro Iwamatsu 17211e32910SNobuhiro Iwamatsu /* SDHI 0 */ 17311e32910SNobuhiro Iwamatsu gpio_request(GPIO_GP_7_17, NULL); 17411e32910SNobuhiro Iwamatsu gpio_request(GPIO_GP_2_12, NULL); 17511e32910SNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ 17611e32910SNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ 17711e32910SNobuhiro Iwamatsu 17811e32910SNobuhiro Iwamatsu ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 17911e32910SNobuhiro Iwamatsu SH_SDHI_QUIRK_16BIT_BUF); 18011e32910SNobuhiro Iwamatsu if (ret) 18111e32910SNobuhiro Iwamatsu return ret; 18211e32910SNobuhiro Iwamatsu 18311e32910SNobuhiro Iwamatsu /* SDHI 1 */ 18411e32910SNobuhiro Iwamatsu gpio_request(GPIO_GP_7_18, NULL); 18511e32910SNobuhiro Iwamatsu gpio_request(GPIO_GP_2_13, NULL); 18611e32910SNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ 18711e32910SNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ 18811e32910SNobuhiro Iwamatsu 18911e32910SNobuhiro Iwamatsu ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); 19011e32910SNobuhiro Iwamatsu if (ret) 19111e32910SNobuhiro Iwamatsu return ret; 19211e32910SNobuhiro Iwamatsu 19311e32910SNobuhiro Iwamatsu /* SDHI 2 */ 19411e32910SNobuhiro Iwamatsu gpio_request(GPIO_GP_7_19, NULL); 19511e32910SNobuhiro Iwamatsu gpio_request(GPIO_GP_2_26, NULL); 19611e32910SNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ 19711e32910SNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ 19811e32910SNobuhiro Iwamatsu 19911e32910SNobuhiro Iwamatsu ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); 20011e32910SNobuhiro Iwamatsu #endif 20111e32910SNobuhiro Iwamatsu return ret; 20211e32910SNobuhiro Iwamatsu } 20311e32910SNobuhiro Iwamatsu 2041251e490SNobuhiro Iwamatsu int dram_init(void) 2051251e490SNobuhiro Iwamatsu { 2061251e490SNobuhiro Iwamatsu gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 2071251e490SNobuhiro Iwamatsu 2081251e490SNobuhiro Iwamatsu return 0; 2091251e490SNobuhiro Iwamatsu } 2101251e490SNobuhiro Iwamatsu 21190362c0cSNobuhiro Iwamatsu /* koelsch has KSZ8041NL/RNL */ 21290362c0cSNobuhiro Iwamatsu #define PHY_CONTROL1 0x1E 21390362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE 0xC0000 21490362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE_ACK 0x4000 21590362c0cSNobuhiro Iwamatsu int board_phy_config(struct phy_device *phydev) 21690362c0cSNobuhiro Iwamatsu { 21790362c0cSNobuhiro Iwamatsu int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 21890362c0cSNobuhiro Iwamatsu ret &= ~PHY_LED_MODE; 21990362c0cSNobuhiro Iwamatsu ret |= PHY_LED_MODE_ACK; 22090362c0cSNobuhiro Iwamatsu ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 22190362c0cSNobuhiro Iwamatsu 22290362c0cSNobuhiro Iwamatsu return 0; 22390362c0cSNobuhiro Iwamatsu } 22490362c0cSNobuhiro Iwamatsu 2251251e490SNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 2261cc95f6eSNobuhiro Iwamatsu CONFIG_ARCH_RMOBILE_BOARD_STRING 2271251e490SNobuhiro Iwamatsu }; 2281251e490SNobuhiro Iwamatsu 2291251e490SNobuhiro Iwamatsu void reset_cpu(ulong addr) 2301251e490SNobuhiro Iwamatsu { 231b8f383b8SNobuhiro Iwamatsu u8 val; 232b8f383b8SNobuhiro Iwamatsu 233b8f383b8SNobuhiro Iwamatsu i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 234b8f383b8SNobuhiro Iwamatsu i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 235b8f383b8SNobuhiro Iwamatsu val |= 0x02; 236b8f383b8SNobuhiro Iwamatsu i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 2371251e490SNobuhiro Iwamatsu } 2380bf51cb0SNobuhiro Iwamatsu 2390bf51cb0SNobuhiro Iwamatsu static const struct sh_serial_platdata serial_platdata = { 2400bf51cb0SNobuhiro Iwamatsu .base = SCIF0_BASE, 2410bf51cb0SNobuhiro Iwamatsu .type = PORT_SCIF, 2420bf51cb0SNobuhiro Iwamatsu .clk = 14745600, 2430bf51cb0SNobuhiro Iwamatsu .clk_mode = EXT_CLK, 2440bf51cb0SNobuhiro Iwamatsu }; 2450bf51cb0SNobuhiro Iwamatsu 2460bf51cb0SNobuhiro Iwamatsu U_BOOT_DEVICE(koelsch_serials) = { 2470bf51cb0SNobuhiro Iwamatsu .name = "serial_sh", 2480bf51cb0SNobuhiro Iwamatsu .platdata = &serial_platdata, 2490bf51cb0SNobuhiro Iwamatsu }; 250