11251e490SNobuhiro Iwamatsu /* 21251e490SNobuhiro Iwamatsu * board/renesas/koelsch/koelsch.c 31251e490SNobuhiro Iwamatsu * 41251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 51251e490SNobuhiro Iwamatsu * 61251e490SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 71251e490SNobuhiro Iwamatsu * 81251e490SNobuhiro Iwamatsu */ 91251e490SNobuhiro Iwamatsu 101251e490SNobuhiro Iwamatsu #include <common.h> 111251e490SNobuhiro Iwamatsu #include <malloc.h> 121251e490SNobuhiro Iwamatsu #include <asm/processor.h> 131251e490SNobuhiro Iwamatsu #include <asm/mach-types.h> 141251e490SNobuhiro Iwamatsu #include <asm/io.h> 151251e490SNobuhiro Iwamatsu #include <asm/errno.h> 161251e490SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 171251e490SNobuhiro Iwamatsu #include <asm/gpio.h> 181251e490SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 1990362c0cSNobuhiro Iwamatsu #include <netdev.h> 2090362c0cSNobuhiro Iwamatsu #include <miiphy.h> 211251e490SNobuhiro Iwamatsu #include <i2c.h> 22ccde6771SNobuhiro Iwamatsu #include <div64.h> 231251e490SNobuhiro Iwamatsu #include "qos.h" 241251e490SNobuhiro Iwamatsu 251251e490SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 261251e490SNobuhiro Iwamatsu 27ccde6771SNobuhiro Iwamatsu #define CLK2MHZ(clk) (clk / 1000 / 1000) 281251e490SNobuhiro Iwamatsu void s_init(void) 291251e490SNobuhiro Iwamatsu { 30ec9b386eSNobuhiro Iwamatsu struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 31ec9b386eSNobuhiro Iwamatsu struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 32ccde6771SNobuhiro Iwamatsu u32 stc; 331251e490SNobuhiro Iwamatsu 341251e490SNobuhiro Iwamatsu /* Watchdog init */ 351251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 361251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 371251e490SNobuhiro Iwamatsu 38ccde6771SNobuhiro Iwamatsu /* CPU frequency setting. Set to 1.5GHz */ 39ccde6771SNobuhiro Iwamatsu stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 40ccde6771SNobuhiro Iwamatsu clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 41ccde6771SNobuhiro Iwamatsu 421251e490SNobuhiro Iwamatsu /* QoS */ 431251e490SNobuhiro Iwamatsu qos_init(); 441251e490SNobuhiro Iwamatsu } 451251e490SNobuhiro Iwamatsu 461251e490SNobuhiro Iwamatsu #define MSTPSR1 0xE6150038 471251e490SNobuhiro Iwamatsu #define SMSTPCR1 0xE6150134 481251e490SNobuhiro Iwamatsu #define TMU0_MSTP125 (1 << 25) 491251e490SNobuhiro Iwamatsu 501251e490SNobuhiro Iwamatsu #define MSTPSR7 0xE61501C4 511251e490SNobuhiro Iwamatsu #define SMSTPCR7 0xE615014C 521251e490SNobuhiro Iwamatsu #define SCIF0_MSTP721 (1 << 21) 531251e490SNobuhiro Iwamatsu 5490362c0cSNobuhiro Iwamatsu #define MSTPSR8 0xE61509A0 5590362c0cSNobuhiro Iwamatsu #define SMSTPCR8 0xE6150990 5690362c0cSNobuhiro Iwamatsu #define ETHER_MSTP813 (1 << 13) 5790362c0cSNobuhiro Iwamatsu 581251e490SNobuhiro Iwamatsu #define mstp_setbits(type, addr, saddr, set) \ 591251e490SNobuhiro Iwamatsu out_##type((saddr), in_##type(addr) | (set)) 601251e490SNobuhiro Iwamatsu #define mstp_clrbits(type, addr, saddr, clear) \ 611251e490SNobuhiro Iwamatsu out_##type((saddr), in_##type(addr) & ~(clear)) 621251e490SNobuhiro Iwamatsu #define mstp_setbits_le32(addr, saddr, set) \ 631251e490SNobuhiro Iwamatsu mstp_setbits(le32, addr, saddr, set) 641251e490SNobuhiro Iwamatsu #define mstp_clrbits_le32(addr, saddr, clear) \ 651251e490SNobuhiro Iwamatsu mstp_clrbits(le32, addr, saddr, clear) 661251e490SNobuhiro Iwamatsu 671251e490SNobuhiro Iwamatsu int board_early_init_f(void) 681251e490SNobuhiro Iwamatsu { 691251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 701251e490SNobuhiro Iwamatsu 711251e490SNobuhiro Iwamatsu /* SCIF0 */ 721251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 731251e490SNobuhiro Iwamatsu 7490362c0cSNobuhiro Iwamatsu /* ETHER */ 7590362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 7690362c0cSNobuhiro Iwamatsu 771251e490SNobuhiro Iwamatsu return 0; 781251e490SNobuhiro Iwamatsu } 791251e490SNobuhiro Iwamatsu 809f861f0aSNobuhiro Iwamatsu void arch_preboot_os(void) 819f861f0aSNobuhiro Iwamatsu { 829f861f0aSNobuhiro Iwamatsu /* Disable TMU0 */ 839f861f0aSNobuhiro Iwamatsu mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 849f861f0aSNobuhiro Iwamatsu } 859f861f0aSNobuhiro Iwamatsu 8690362c0cSNobuhiro Iwamatsu /* LSI pin pull-up control */ 8790362c0cSNobuhiro Iwamatsu #define PUPR5 0xe6060114 8890362c0cSNobuhiro Iwamatsu #define PUPR5_ETH 0x3FFC0000 8990362c0cSNobuhiro Iwamatsu #define PUPR5_ETH_MAGIC (1 << 27) 901251e490SNobuhiro Iwamatsu int board_init(void) 911251e490SNobuhiro Iwamatsu { 921251e490SNobuhiro Iwamatsu /* adress of boot parameters */ 93*956556fbSNobuhiro Iwamatsu gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 941251e490SNobuhiro Iwamatsu 951251e490SNobuhiro Iwamatsu /* Init PFC controller */ 961251e490SNobuhiro Iwamatsu r8a7791_pinmux_init(); 971251e490SNobuhiro Iwamatsu 9890362c0cSNobuhiro Iwamatsu /* ETHER Enable */ 9990362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 10090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RX_ER, NULL); 10190362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD0, NULL); 10290362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_RXD1, NULL); 10390362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_LINK, NULL); 10490362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_REFCLK, NULL); 10590362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDIO, NULL); 10690362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD1, NULL); 10790362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TX_EN, NULL); 10890362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_TXD0, NULL); 10990362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_ETH_MDC, NULL); 11090362c0cSNobuhiro Iwamatsu gpio_request(GPIO_FN_IRQ0, NULL); 11190362c0cSNobuhiro Iwamatsu 11290362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); 11390362c0cSNobuhiro Iwamatsu gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ 11490362c0cSNobuhiro Iwamatsu mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); 11590362c0cSNobuhiro Iwamatsu 11690362c0cSNobuhiro Iwamatsu gpio_direction_output(GPIO_GP_5_22, 0); 11790362c0cSNobuhiro Iwamatsu mdelay(20); 11890362c0cSNobuhiro Iwamatsu gpio_set_value(GPIO_GP_5_22, 1); 11990362c0cSNobuhiro Iwamatsu udelay(1); 12090362c0cSNobuhiro Iwamatsu 1211251e490SNobuhiro Iwamatsu return 0; 1221251e490SNobuhiro Iwamatsu } 1231251e490SNobuhiro Iwamatsu 12490362c0cSNobuhiro Iwamatsu #define CXR24 0xEE7003C0 /* MAC address high register */ 12590362c0cSNobuhiro Iwamatsu #define CXR25 0xEE7003C8 /* MAC address low register */ 12690362c0cSNobuhiro Iwamatsu int board_eth_init(bd_t *bis) 12790362c0cSNobuhiro Iwamatsu { 12890362c0cSNobuhiro Iwamatsu #ifdef CONFIG_SH_ETHER 12990362c0cSNobuhiro Iwamatsu int ret = -ENODEV; 13090362c0cSNobuhiro Iwamatsu u32 val; 13190362c0cSNobuhiro Iwamatsu unsigned char enetaddr[6]; 13290362c0cSNobuhiro Iwamatsu 13390362c0cSNobuhiro Iwamatsu ret = sh_eth_initialize(bis); 13490362c0cSNobuhiro Iwamatsu if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 13590362c0cSNobuhiro Iwamatsu return ret; 13690362c0cSNobuhiro Iwamatsu 13790362c0cSNobuhiro Iwamatsu /* Set Mac address */ 13890362c0cSNobuhiro Iwamatsu val = enetaddr[0] << 24 | enetaddr[1] << 16 | 13990362c0cSNobuhiro Iwamatsu enetaddr[2] << 8 | enetaddr[3]; 14090362c0cSNobuhiro Iwamatsu writel(val, CXR24); 14190362c0cSNobuhiro Iwamatsu 14290362c0cSNobuhiro Iwamatsu val = enetaddr[4] << 8 | enetaddr[5]; 14390362c0cSNobuhiro Iwamatsu writel(val, CXR25); 14490362c0cSNobuhiro Iwamatsu 14590362c0cSNobuhiro Iwamatsu return ret; 14690362c0cSNobuhiro Iwamatsu #else 14790362c0cSNobuhiro Iwamatsu return 0; 14890362c0cSNobuhiro Iwamatsu #endif 14990362c0cSNobuhiro Iwamatsu } 15090362c0cSNobuhiro Iwamatsu 1511251e490SNobuhiro Iwamatsu int dram_init(void) 1521251e490SNobuhiro Iwamatsu { 1531251e490SNobuhiro Iwamatsu gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 1541251e490SNobuhiro Iwamatsu 1551251e490SNobuhiro Iwamatsu return 0; 1561251e490SNobuhiro Iwamatsu } 1571251e490SNobuhiro Iwamatsu 15890362c0cSNobuhiro Iwamatsu /* koelsch has KSZ8041NL/RNL */ 15990362c0cSNobuhiro Iwamatsu #define PHY_CONTROL1 0x1E 16090362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE 0xC0000 16190362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE_ACK 0x4000 16290362c0cSNobuhiro Iwamatsu int board_phy_config(struct phy_device *phydev) 16390362c0cSNobuhiro Iwamatsu { 16490362c0cSNobuhiro Iwamatsu int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 16590362c0cSNobuhiro Iwamatsu ret &= ~PHY_LED_MODE; 16690362c0cSNobuhiro Iwamatsu ret |= PHY_LED_MODE_ACK; 16790362c0cSNobuhiro Iwamatsu ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 16890362c0cSNobuhiro Iwamatsu 16990362c0cSNobuhiro Iwamatsu return 0; 17090362c0cSNobuhiro Iwamatsu } 17190362c0cSNobuhiro Iwamatsu 1721251e490SNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 1731251e490SNobuhiro Iwamatsu CONFIG_RMOBILE_BOARD_STRING 1741251e490SNobuhiro Iwamatsu }; 1751251e490SNobuhiro Iwamatsu 1761251e490SNobuhiro Iwamatsu void reset_cpu(ulong addr) 1771251e490SNobuhiro Iwamatsu { 178b8f383b8SNobuhiro Iwamatsu u8 val; 179b8f383b8SNobuhiro Iwamatsu 180b8f383b8SNobuhiro Iwamatsu i2c_set_bus_num(2); /* PowerIC connected to ch2 */ 181b8f383b8SNobuhiro Iwamatsu i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 182b8f383b8SNobuhiro Iwamatsu val |= 0x02; 183b8f383b8SNobuhiro Iwamatsu i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 1841251e490SNobuhiro Iwamatsu } 185