11251e490SNobuhiro Iwamatsu /* 21251e490SNobuhiro Iwamatsu * board/renesas/koelsch/koelsch.c 31251e490SNobuhiro Iwamatsu * 41251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 51251e490SNobuhiro Iwamatsu * 61251e490SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 71251e490SNobuhiro Iwamatsu * 81251e490SNobuhiro Iwamatsu */ 91251e490SNobuhiro Iwamatsu 101251e490SNobuhiro Iwamatsu #include <common.h> 111251e490SNobuhiro Iwamatsu #include <malloc.h> 120bf51cb0SNobuhiro Iwamatsu #include <dm.h> 130bf51cb0SNobuhiro Iwamatsu #include <dm/platform_data/serial_sh.h> 149925f1dbSAlex Kiernan #include <environment.h> 151251e490SNobuhiro Iwamatsu #include <asm/processor.h> 161251e490SNobuhiro Iwamatsu #include <asm/mach-types.h> 171251e490SNobuhiro Iwamatsu #include <asm/io.h> 181221ce45SMasahiro Yamada #include <linux/errno.h> 191251e490SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 201251e490SNobuhiro Iwamatsu #include <asm/gpio.h> 211251e490SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 2244e1eebfSNobuhiro Iwamatsu #include <asm/arch/rcar-mstp.h> 2311e32910SNobuhiro Iwamatsu #include <asm/arch/sh_sdhi.h> 2490362c0cSNobuhiro Iwamatsu #include <netdev.h> 2590362c0cSNobuhiro Iwamatsu #include <miiphy.h> 261251e490SNobuhiro Iwamatsu #include <i2c.h> 27ccde6771SNobuhiro Iwamatsu #include <div64.h> 281251e490SNobuhiro Iwamatsu #include "qos.h" 291251e490SNobuhiro Iwamatsu 301251e490SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 311251e490SNobuhiro Iwamatsu 32ccde6771SNobuhiro Iwamatsu #define CLK2MHZ(clk) (clk / 1000 / 1000) 331251e490SNobuhiro Iwamatsu void s_init(void) 341251e490SNobuhiro Iwamatsu { 35ec9b386eSNobuhiro Iwamatsu struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 36ec9b386eSNobuhiro Iwamatsu struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 37ccde6771SNobuhiro Iwamatsu u32 stc; 381251e490SNobuhiro Iwamatsu 391251e490SNobuhiro Iwamatsu /* Watchdog init */ 401251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 411251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 421251e490SNobuhiro Iwamatsu 43ccde6771SNobuhiro Iwamatsu /* CPU frequency setting. Set to 1.5GHz */ 44ccde6771SNobuhiro Iwamatsu stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 45ccde6771SNobuhiro Iwamatsu clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 46ccde6771SNobuhiro Iwamatsu 471251e490SNobuhiro Iwamatsu /* QoS */ 481251e490SNobuhiro Iwamatsu qos_init(); 491251e490SNobuhiro Iwamatsu } 501251e490SNobuhiro Iwamatsu 51*7d0299cdSMarek Vasut #define TMU0_MSTP125 BIT(25) 5211e32910SNobuhiro Iwamatsu 5311e32910SNobuhiro Iwamatsu #define SD1CKCR 0xE6150078 5411e32910SNobuhiro Iwamatsu #define SD2CKCR 0xE615026C 5511e32910SNobuhiro Iwamatsu #define SD_97500KHZ 0x7 5611e32910SNobuhiro Iwamatsu 571251e490SNobuhiro Iwamatsu int board_early_init_f(void) 581251e490SNobuhiro Iwamatsu { 591251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 601251e490SNobuhiro Iwamatsu 6111e32910SNobuhiro Iwamatsu /* 6211e32910SNobuhiro Iwamatsu * SD0 clock is set to 97.5MHz by default. 6311e32910SNobuhiro Iwamatsu * Set SD1 and SD2 to the 97.5MHz as well. 6411e32910SNobuhiro Iwamatsu */ 6511e32910SNobuhiro Iwamatsu writel(SD_97500KHZ, SD1CKCR); 6611e32910SNobuhiro Iwamatsu writel(SD_97500KHZ, SD2CKCR); 6711e32910SNobuhiro Iwamatsu 681251e490SNobuhiro Iwamatsu return 0; 691251e490SNobuhiro Iwamatsu } 701251e490SNobuhiro Iwamatsu 71*7d0299cdSMarek Vasut #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ 72*7d0299cdSMarek Vasut 731251e490SNobuhiro Iwamatsu int board_init(void) 741251e490SNobuhiro Iwamatsu { 751251e490SNobuhiro Iwamatsu /* adress of boot parameters */ 76956556fbSNobuhiro Iwamatsu gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 771251e490SNobuhiro Iwamatsu 78*7d0299cdSMarek Vasut /* Force ethernet PHY out of reset */ 79*7d0299cdSMarek Vasut gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 80*7d0299cdSMarek Vasut gpio_direction_output(ETHERNET_PHY_RESET, 0); 81*7d0299cdSMarek Vasut mdelay(10); 82*7d0299cdSMarek Vasut gpio_direction_output(ETHERNET_PHY_RESET, 1); 8390362c0cSNobuhiro Iwamatsu 841251e490SNobuhiro Iwamatsu return 0; 851251e490SNobuhiro Iwamatsu } 861251e490SNobuhiro Iwamatsu 871251e490SNobuhiro Iwamatsu int dram_init(void) 881251e490SNobuhiro Iwamatsu { 89*7d0299cdSMarek Vasut if (fdtdec_setup_memory_size() != 0) 90*7d0299cdSMarek Vasut return -EINVAL; 911251e490SNobuhiro Iwamatsu 921251e490SNobuhiro Iwamatsu return 0; 931251e490SNobuhiro Iwamatsu } 941251e490SNobuhiro Iwamatsu 95*7d0299cdSMarek Vasut int dram_init_banksize(void) 96*7d0299cdSMarek Vasut { 97*7d0299cdSMarek Vasut fdtdec_setup_memory_banksize(); 98*7d0299cdSMarek Vasut 99*7d0299cdSMarek Vasut return 0; 100*7d0299cdSMarek Vasut } 101*7d0299cdSMarek Vasut 102*7d0299cdSMarek Vasut /* Koelsch has KSZ8041NL/RNL */ 10390362c0cSNobuhiro Iwamatsu #define PHY_CONTROL1 0x1E 10490362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE 0xC0000 10590362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE_ACK 0x4000 10690362c0cSNobuhiro Iwamatsu int board_phy_config(struct phy_device *phydev) 10790362c0cSNobuhiro Iwamatsu { 10890362c0cSNobuhiro Iwamatsu int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 10990362c0cSNobuhiro Iwamatsu ret &= ~PHY_LED_MODE; 11090362c0cSNobuhiro Iwamatsu ret |= PHY_LED_MODE_ACK; 11190362c0cSNobuhiro Iwamatsu ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 11290362c0cSNobuhiro Iwamatsu 11390362c0cSNobuhiro Iwamatsu return 0; 11490362c0cSNobuhiro Iwamatsu } 11590362c0cSNobuhiro Iwamatsu 1161251e490SNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 1171cc95f6eSNobuhiro Iwamatsu CONFIG_ARCH_RMOBILE_BOARD_STRING 1181251e490SNobuhiro Iwamatsu }; 1191251e490SNobuhiro Iwamatsu 1201251e490SNobuhiro Iwamatsu void reset_cpu(ulong addr) 1211251e490SNobuhiro Iwamatsu { 122*7d0299cdSMarek Vasut struct udevice *dev; 123*7d0299cdSMarek Vasut const u8 pmic_bus = 6; 124*7d0299cdSMarek Vasut const u8 pmic_addr = 0x58; 125*7d0299cdSMarek Vasut u8 data; 126*7d0299cdSMarek Vasut int ret; 127b8f383b8SNobuhiro Iwamatsu 128*7d0299cdSMarek Vasut ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 129*7d0299cdSMarek Vasut if (ret) 130*7d0299cdSMarek Vasut hang(); 131*7d0299cdSMarek Vasut 132*7d0299cdSMarek Vasut ret = dm_i2c_read(dev, 0x13, &data, 1); 133*7d0299cdSMarek Vasut if (ret) 134*7d0299cdSMarek Vasut hang(); 135*7d0299cdSMarek Vasut 136*7d0299cdSMarek Vasut data |= BIT(1); 137*7d0299cdSMarek Vasut 138*7d0299cdSMarek Vasut ret = dm_i2c_write(dev, 0x13, &data, 1); 139*7d0299cdSMarek Vasut if (ret) 140*7d0299cdSMarek Vasut hang(); 1411251e490SNobuhiro Iwamatsu } 1420bf51cb0SNobuhiro Iwamatsu 143*7d0299cdSMarek Vasut enum env_location env_get_location(enum env_operation op, int prio) 144*7d0299cdSMarek Vasut { 145*7d0299cdSMarek Vasut const u32 load_magic = 0xb33fc0de; 1460bf51cb0SNobuhiro Iwamatsu 147*7d0299cdSMarek Vasut /* Block environment access if loaded using JTAG */ 148*7d0299cdSMarek Vasut if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 149*7d0299cdSMarek Vasut (op != ENVOP_INIT)) 150*7d0299cdSMarek Vasut return ENVL_UNKNOWN; 151*7d0299cdSMarek Vasut 152*7d0299cdSMarek Vasut if (prio) 153*7d0299cdSMarek Vasut return ENVL_UNKNOWN; 154*7d0299cdSMarek Vasut 155*7d0299cdSMarek Vasut return ENVL_SPI_FLASH; 156*7d0299cdSMarek Vasut } 157