183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 21251e490SNobuhiro Iwamatsu /* 31251e490SNobuhiro Iwamatsu * board/renesas/koelsch/koelsch.c 41251e490SNobuhiro Iwamatsu * 51251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 61251e490SNobuhiro Iwamatsu * 71251e490SNobuhiro Iwamatsu */ 81251e490SNobuhiro Iwamatsu 91251e490SNobuhiro Iwamatsu #include <common.h> 101251e490SNobuhiro Iwamatsu #include <malloc.h> 110bf51cb0SNobuhiro Iwamatsu #include <dm.h> 120bf51cb0SNobuhiro Iwamatsu #include <dm/platform_data/serial_sh.h> 139925f1dbSAlex Kiernan #include <environment.h> 141251e490SNobuhiro Iwamatsu #include <asm/processor.h> 151251e490SNobuhiro Iwamatsu #include <asm/mach-types.h> 161251e490SNobuhiro Iwamatsu #include <asm/io.h> 171221ce45SMasahiro Yamada #include <linux/errno.h> 181251e490SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 191251e490SNobuhiro Iwamatsu #include <asm/gpio.h> 201251e490SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 2144e1eebfSNobuhiro Iwamatsu #include <asm/arch/rcar-mstp.h> 2211e32910SNobuhiro Iwamatsu #include <asm/arch/sh_sdhi.h> 2390362c0cSNobuhiro Iwamatsu #include <netdev.h> 2490362c0cSNobuhiro Iwamatsu #include <miiphy.h> 251251e490SNobuhiro Iwamatsu #include <i2c.h> 26ccde6771SNobuhiro Iwamatsu #include <div64.h> 271251e490SNobuhiro Iwamatsu #include "qos.h" 281251e490SNobuhiro Iwamatsu 291251e490SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 301251e490SNobuhiro Iwamatsu 31ccde6771SNobuhiro Iwamatsu #define CLK2MHZ(clk) (clk / 1000 / 1000) 321251e490SNobuhiro Iwamatsu void s_init(void) 331251e490SNobuhiro Iwamatsu { 34ec9b386eSNobuhiro Iwamatsu struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 35ec9b386eSNobuhiro Iwamatsu struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 36ccde6771SNobuhiro Iwamatsu u32 stc; 371251e490SNobuhiro Iwamatsu 381251e490SNobuhiro Iwamatsu /* Watchdog init */ 391251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 401251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 411251e490SNobuhiro Iwamatsu 42ccde6771SNobuhiro Iwamatsu /* CPU frequency setting. Set to 1.5GHz */ 43ccde6771SNobuhiro Iwamatsu stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 44ccde6771SNobuhiro Iwamatsu clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 45ccde6771SNobuhiro Iwamatsu 461251e490SNobuhiro Iwamatsu /* QoS */ 471251e490SNobuhiro Iwamatsu qos_init(); 481251e490SNobuhiro Iwamatsu } 491251e490SNobuhiro Iwamatsu 507d0299cdSMarek Vasut #define TMU0_MSTP125 BIT(25) 5111e32910SNobuhiro Iwamatsu 5211e32910SNobuhiro Iwamatsu #define SD1CKCR 0xE6150078 5311e32910SNobuhiro Iwamatsu #define SD2CKCR 0xE615026C 5411e32910SNobuhiro Iwamatsu #define SD_97500KHZ 0x7 5511e32910SNobuhiro Iwamatsu 561251e490SNobuhiro Iwamatsu int board_early_init_f(void) 571251e490SNobuhiro Iwamatsu { 581251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 591251e490SNobuhiro Iwamatsu 6011e32910SNobuhiro Iwamatsu /* 6111e32910SNobuhiro Iwamatsu * SD0 clock is set to 97.5MHz by default. 6211e32910SNobuhiro Iwamatsu * Set SD1 and SD2 to the 97.5MHz as well. 6311e32910SNobuhiro Iwamatsu */ 6411e32910SNobuhiro Iwamatsu writel(SD_97500KHZ, SD1CKCR); 6511e32910SNobuhiro Iwamatsu writel(SD_97500KHZ, SD2CKCR); 6611e32910SNobuhiro Iwamatsu 671251e490SNobuhiro Iwamatsu return 0; 681251e490SNobuhiro Iwamatsu } 691251e490SNobuhiro Iwamatsu 707d0299cdSMarek Vasut #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ 717d0299cdSMarek Vasut 721251e490SNobuhiro Iwamatsu int board_init(void) 731251e490SNobuhiro Iwamatsu { 741251e490SNobuhiro Iwamatsu /* adress of boot parameters */ 75956556fbSNobuhiro Iwamatsu gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 761251e490SNobuhiro Iwamatsu 777d0299cdSMarek Vasut /* Force ethernet PHY out of reset */ 787d0299cdSMarek Vasut gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 797d0299cdSMarek Vasut gpio_direction_output(ETHERNET_PHY_RESET, 0); 807d0299cdSMarek Vasut mdelay(10); 817d0299cdSMarek Vasut gpio_direction_output(ETHERNET_PHY_RESET, 1); 8290362c0cSNobuhiro Iwamatsu 831251e490SNobuhiro Iwamatsu return 0; 841251e490SNobuhiro Iwamatsu } 851251e490SNobuhiro Iwamatsu 861251e490SNobuhiro Iwamatsu int dram_init(void) 871251e490SNobuhiro Iwamatsu { 8812308b12SSiva Durga Prasad Paladugu if (fdtdec_setup_mem_size_base() != 0) 897d0299cdSMarek Vasut return -EINVAL; 901251e490SNobuhiro Iwamatsu 911251e490SNobuhiro Iwamatsu return 0; 921251e490SNobuhiro Iwamatsu } 931251e490SNobuhiro Iwamatsu 947d0299cdSMarek Vasut int dram_init_banksize(void) 957d0299cdSMarek Vasut { 967d0299cdSMarek Vasut fdtdec_setup_memory_banksize(); 977d0299cdSMarek Vasut 987d0299cdSMarek Vasut return 0; 997d0299cdSMarek Vasut } 1007d0299cdSMarek Vasut 1017d0299cdSMarek Vasut /* Koelsch has KSZ8041NL/RNL */ 10290362c0cSNobuhiro Iwamatsu #define PHY_CONTROL1 0x1E 103*4bbd4642SMarek Vasut #define PHY_LED_MODE 0xC000 10490362c0cSNobuhiro Iwamatsu #define PHY_LED_MODE_ACK 0x4000 10590362c0cSNobuhiro Iwamatsu int board_phy_config(struct phy_device *phydev) 10690362c0cSNobuhiro Iwamatsu { 10790362c0cSNobuhiro Iwamatsu int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 10890362c0cSNobuhiro Iwamatsu ret &= ~PHY_LED_MODE; 10990362c0cSNobuhiro Iwamatsu ret |= PHY_LED_MODE_ACK; 11090362c0cSNobuhiro Iwamatsu ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 11190362c0cSNobuhiro Iwamatsu 11290362c0cSNobuhiro Iwamatsu return 0; 11390362c0cSNobuhiro Iwamatsu } 11490362c0cSNobuhiro Iwamatsu 1151251e490SNobuhiro Iwamatsu void reset_cpu(ulong addr) 1161251e490SNobuhiro Iwamatsu { 1177d0299cdSMarek Vasut struct udevice *dev; 1187d0299cdSMarek Vasut const u8 pmic_bus = 6; 1197d0299cdSMarek Vasut const u8 pmic_addr = 0x58; 1207d0299cdSMarek Vasut u8 data; 1217d0299cdSMarek Vasut int ret; 122b8f383b8SNobuhiro Iwamatsu 1237d0299cdSMarek Vasut ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 1247d0299cdSMarek Vasut if (ret) 1257d0299cdSMarek Vasut hang(); 1267d0299cdSMarek Vasut 1277d0299cdSMarek Vasut ret = dm_i2c_read(dev, 0x13, &data, 1); 1287d0299cdSMarek Vasut if (ret) 1297d0299cdSMarek Vasut hang(); 1307d0299cdSMarek Vasut 1317d0299cdSMarek Vasut data |= BIT(1); 1327d0299cdSMarek Vasut 1337d0299cdSMarek Vasut ret = dm_i2c_write(dev, 0x13, &data, 1); 1347d0299cdSMarek Vasut if (ret) 1357d0299cdSMarek Vasut hang(); 1361251e490SNobuhiro Iwamatsu } 1370bf51cb0SNobuhiro Iwamatsu 1387d0299cdSMarek Vasut enum env_location env_get_location(enum env_operation op, int prio) 1397d0299cdSMarek Vasut { 1407d0299cdSMarek Vasut const u32 load_magic = 0xb33fc0de; 1410bf51cb0SNobuhiro Iwamatsu 1427d0299cdSMarek Vasut /* Block environment access if loaded using JTAG */ 1437d0299cdSMarek Vasut if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 1447d0299cdSMarek Vasut (op != ENVOP_INIT)) 1457d0299cdSMarek Vasut return ENVL_UNKNOWN; 1467d0299cdSMarek Vasut 1477d0299cdSMarek Vasut if (prio) 1487d0299cdSMarek Vasut return ENVL_UNKNOWN; 1497d0299cdSMarek Vasut 1507d0299cdSMarek Vasut return ENVL_SPI_FLASH; 1517d0299cdSMarek Vasut } 152