1*1251e490SNobuhiro Iwamatsu /* 2*1251e490SNobuhiro Iwamatsu * board/renesas/koelsch/koelsch.c 3*1251e490SNobuhiro Iwamatsu * 4*1251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 5*1251e490SNobuhiro Iwamatsu * 6*1251e490SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 7*1251e490SNobuhiro Iwamatsu * 8*1251e490SNobuhiro Iwamatsu */ 9*1251e490SNobuhiro Iwamatsu 10*1251e490SNobuhiro Iwamatsu #include <common.h> 11*1251e490SNobuhiro Iwamatsu #include <malloc.h> 12*1251e490SNobuhiro Iwamatsu #include <asm/processor.h> 13*1251e490SNobuhiro Iwamatsu #include <asm/mach-types.h> 14*1251e490SNobuhiro Iwamatsu #include <asm/io.h> 15*1251e490SNobuhiro Iwamatsu #include <asm/errno.h> 16*1251e490SNobuhiro Iwamatsu #include <asm/arch/sys_proto.h> 17*1251e490SNobuhiro Iwamatsu #include <asm/gpio.h> 18*1251e490SNobuhiro Iwamatsu #include <asm/arch/rmobile.h> 19*1251e490SNobuhiro Iwamatsu #include <i2c.h> 20*1251e490SNobuhiro Iwamatsu #include "qos.h" 21*1251e490SNobuhiro Iwamatsu 22*1251e490SNobuhiro Iwamatsu DECLARE_GLOBAL_DATA_PTR; 23*1251e490SNobuhiro Iwamatsu 24*1251e490SNobuhiro Iwamatsu #define s_init_wait(cnt) \ 25*1251e490SNobuhiro Iwamatsu ({ \ 26*1251e490SNobuhiro Iwamatsu u32 i = 0x10000 * cnt; \ 27*1251e490SNobuhiro Iwamatsu while (i > 0) \ 28*1251e490SNobuhiro Iwamatsu i--; \ 29*1251e490SNobuhiro Iwamatsu }) 30*1251e490SNobuhiro Iwamatsu 31*1251e490SNobuhiro Iwamatsu 32*1251e490SNobuhiro Iwamatsu #define dbpdrgd_check(bsc) \ 33*1251e490SNobuhiro Iwamatsu ({ \ 34*1251e490SNobuhiro Iwamatsu while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \ 35*1251e490SNobuhiro Iwamatsu ; \ 36*1251e490SNobuhiro Iwamatsu }) 37*1251e490SNobuhiro Iwamatsu 38*1251e490SNobuhiro Iwamatsu #if defined(CONFIG_NORFLASH) 39*1251e490SNobuhiro Iwamatsu static void bsc_init(void) 40*1251e490SNobuhiro Iwamatsu { 41*1251e490SNobuhiro Iwamatsu struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE; 42*1251e490SNobuhiro Iwamatsu struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE; 43*1251e490SNobuhiro Iwamatsu 44*1251e490SNobuhiro Iwamatsu /* LBSC */ 45*1251e490SNobuhiro Iwamatsu writel(0x00000020, &lbsc->cs0ctrl); 46*1251e490SNobuhiro Iwamatsu writel(0x00000020, &lbsc->cs1ctrl); 47*1251e490SNobuhiro Iwamatsu writel(0x00002020, &lbsc->ecs0ctrl); 48*1251e490SNobuhiro Iwamatsu writel(0x00002020, &lbsc->ecs1ctrl); 49*1251e490SNobuhiro Iwamatsu 50*1251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->cswcr0); 51*1251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->cswcr1); 52*1251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->ecswcr0); 53*1251e490SNobuhiro Iwamatsu writel(0x077F077F, &lbsc->ecswcr1); 54*1251e490SNobuhiro Iwamatsu 55*1251e490SNobuhiro Iwamatsu /* DBSC3 */ 56*1251e490SNobuhiro Iwamatsu s_init_wait(10); 57*1251e490SNobuhiro Iwamatsu 58*1251e490SNobuhiro Iwamatsu writel(0x0000A55A, &dbsc3_0->dbpdlck); 59*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 60*1251e490SNobuhiro Iwamatsu writel(0x80000000, &dbsc3_0->dbpdrgd); 61*1251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 62*1251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 63*1251e490SNobuhiro Iwamatsu 64*1251e490SNobuhiro Iwamatsu writel(0x00000006, &dbsc3_0->dbpdrga); 65*1251e490SNobuhiro Iwamatsu writel(0x0001C000, &dbsc3_0->dbpdrgd); 66*1251e490SNobuhiro Iwamatsu 67*1251e490SNobuhiro Iwamatsu writel(0x00000023, &dbsc3_0->dbpdrga); 68*1251e490SNobuhiro Iwamatsu writel(0x00FD2480, &dbsc3_0->dbpdrgd); 69*1251e490SNobuhiro Iwamatsu 70*1251e490SNobuhiro Iwamatsu writel(0x00000010, &dbsc3_0->dbpdrga); 71*1251e490SNobuhiro Iwamatsu writel(0xF004649B, &dbsc3_0->dbpdrgd); 72*1251e490SNobuhiro Iwamatsu 73*1251e490SNobuhiro Iwamatsu writel(0x0000000F, &dbsc3_0->dbpdrga); 74*1251e490SNobuhiro Iwamatsu writel(0x00181EE4, &dbsc3_0->dbpdrgd); 75*1251e490SNobuhiro Iwamatsu 76*1251e490SNobuhiro Iwamatsu writel(0x0000000E, &dbsc3_0->dbpdrga); 77*1251e490SNobuhiro Iwamatsu writel(0x33C03812, &dbsc3_0->dbpdrgd); 78*1251e490SNobuhiro Iwamatsu 79*1251e490SNobuhiro Iwamatsu writel(0x00000003, &dbsc3_0->dbpdrga); 80*1251e490SNobuhiro Iwamatsu writel(0x0300C481, &dbsc3_0->dbpdrgd); 81*1251e490SNobuhiro Iwamatsu 82*1251e490SNobuhiro Iwamatsu writel(0x00000007, &dbsc3_0->dbkind); 83*1251e490SNobuhiro Iwamatsu writel(0x10030A02, &dbsc3_0->dbconf0); 84*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbphytype); 85*1251e490SNobuhiro Iwamatsu writel(0x00000000, &dbsc3_0->dbbl); 86*1251e490SNobuhiro Iwamatsu writel(0x0000000B, &dbsc3_0->dbtr0); 87*1251e490SNobuhiro Iwamatsu writel(0x00000008, &dbsc3_0->dbtr1); 88*1251e490SNobuhiro Iwamatsu writel(0x00000000, &dbsc3_0->dbtr2); 89*1251e490SNobuhiro Iwamatsu writel(0x0000000B, &dbsc3_0->dbtr3); 90*1251e490SNobuhiro Iwamatsu writel(0x000C000B, &dbsc3_0->dbtr4); 91*1251e490SNobuhiro Iwamatsu writel(0x00000027, &dbsc3_0->dbtr5); 92*1251e490SNobuhiro Iwamatsu writel(0x0000001C, &dbsc3_0->dbtr6); 93*1251e490SNobuhiro Iwamatsu writel(0x00000005, &dbsc3_0->dbtr7); 94*1251e490SNobuhiro Iwamatsu writel(0x00000018, &dbsc3_0->dbtr8); 95*1251e490SNobuhiro Iwamatsu writel(0x00000008, &dbsc3_0->dbtr9); 96*1251e490SNobuhiro Iwamatsu writel(0x0000000C, &dbsc3_0->dbtr10); 97*1251e490SNobuhiro Iwamatsu writel(0x00000009, &dbsc3_0->dbtr11); 98*1251e490SNobuhiro Iwamatsu writel(0x00000012, &dbsc3_0->dbtr12); 99*1251e490SNobuhiro Iwamatsu writel(0x000000D0, &dbsc3_0->dbtr13); 100*1251e490SNobuhiro Iwamatsu writel(0x00140005, &dbsc3_0->dbtr14); 101*1251e490SNobuhiro Iwamatsu writel(0x00050004, &dbsc3_0->dbtr15); 102*1251e490SNobuhiro Iwamatsu writel(0x70233005, &dbsc3_0->dbtr16); 103*1251e490SNobuhiro Iwamatsu writel(0x000C0000, &dbsc3_0->dbtr17); 104*1251e490SNobuhiro Iwamatsu writel(0x00000300, &dbsc3_0->dbtr18); 105*1251e490SNobuhiro Iwamatsu writel(0x00000040, &dbsc3_0->dbtr19); 106*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbrnk0); 107*1251e490SNobuhiro Iwamatsu writel(0x00020001, &dbsc3_0->dbadj0); 108*1251e490SNobuhiro Iwamatsu writel(0x20082008, &dbsc3_0->dbadj2); 109*1251e490SNobuhiro Iwamatsu writel(0x00020002, &dbsc3_0->dbwt0cnf0); 110*1251e490SNobuhiro Iwamatsu writel(0x0000000F, &dbsc3_0->dbwt0cnf4); 111*1251e490SNobuhiro Iwamatsu 112*1251e490SNobuhiro Iwamatsu writel(0x00000015, &dbsc3_0->dbpdrga); 113*1251e490SNobuhiro Iwamatsu writel(0x00000D70, &dbsc3_0->dbpdrgd); 114*1251e490SNobuhiro Iwamatsu 115*1251e490SNobuhiro Iwamatsu writel(0x00000016, &dbsc3_0->dbpdrga); 116*1251e490SNobuhiro Iwamatsu writel(0x00000006, &dbsc3_0->dbpdrgd); 117*1251e490SNobuhiro Iwamatsu 118*1251e490SNobuhiro Iwamatsu writel(0x00000017, &dbsc3_0->dbpdrga); 119*1251e490SNobuhiro Iwamatsu writel(0x00000018, &dbsc3_0->dbpdrgd); 120*1251e490SNobuhiro Iwamatsu 121*1251e490SNobuhiro Iwamatsu writel(0x00000012, &dbsc3_0->dbpdrga); 122*1251e490SNobuhiro Iwamatsu writel(0x9D5CBB66, &dbsc3_0->dbpdrgd); 123*1251e490SNobuhiro Iwamatsu 124*1251e490SNobuhiro Iwamatsu writel(0x00000013, &dbsc3_0->dbpdrga); 125*1251e490SNobuhiro Iwamatsu writel(0x1A868300, &dbsc3_0->dbpdrgd); 126*1251e490SNobuhiro Iwamatsu 127*1251e490SNobuhiro Iwamatsu writel(0x00000023, &dbsc3_0->dbpdrga); 128*1251e490SNobuhiro Iwamatsu writel(0x00FDB6C0, &dbsc3_0->dbpdrgd); 129*1251e490SNobuhiro Iwamatsu 130*1251e490SNobuhiro Iwamatsu writel(0x00000014, &dbsc3_0->dbpdrga); 131*1251e490SNobuhiro Iwamatsu writel(0x300214D8, &dbsc3_0->dbpdrgd); 132*1251e490SNobuhiro Iwamatsu 133*1251e490SNobuhiro Iwamatsu writel(0x0000001A, &dbsc3_0->dbpdrga); 134*1251e490SNobuhiro Iwamatsu writel(0x930035C7, &dbsc3_0->dbpdrgd); 135*1251e490SNobuhiro Iwamatsu 136*1251e490SNobuhiro Iwamatsu writel(0x00000060, &dbsc3_0->dbpdrga); 137*1251e490SNobuhiro Iwamatsu writel(0x330657B2, &dbsc3_0->dbpdrgd); 138*1251e490SNobuhiro Iwamatsu 139*1251e490SNobuhiro Iwamatsu writel(0x00000011, &dbsc3_0->dbpdrga); 140*1251e490SNobuhiro Iwamatsu writel(0x1000040B, &dbsc3_0->dbpdrgd); 141*1251e490SNobuhiro Iwamatsu 142*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 143*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 144*1251e490SNobuhiro Iwamatsu writel(0x00000071, &dbsc3_0->dbpdrgd); 145*1251e490SNobuhiro Iwamatsu 146*1251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 147*1251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 148*1251e490SNobuhiro Iwamatsu 149*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 150*1251e490SNobuhiro Iwamatsu writel(0x2100FA00, &dbsc3_0->dbcmd); 151*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 152*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 153*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 154*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 155*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 156*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 157*1251e490SNobuhiro Iwamatsu writel(0x0000FA00, &dbsc3_0->dbcmd); 158*1251e490SNobuhiro Iwamatsu 159*1251e490SNobuhiro Iwamatsu writel(0x110000DB, &dbsc3_0->dbcmd); 160*1251e490SNobuhiro Iwamatsu 161*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 162*1251e490SNobuhiro Iwamatsu writel(0x00000181, &dbsc3_0->dbpdrgd); 163*1251e490SNobuhiro Iwamatsu 164*1251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 165*1251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 166*1251e490SNobuhiro Iwamatsu 167*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbpdrga); 168*1251e490SNobuhiro Iwamatsu writel(0x0000FE01, &dbsc3_0->dbpdrgd); 169*1251e490SNobuhiro Iwamatsu 170*1251e490SNobuhiro Iwamatsu writel(0x00000004, &dbsc3_0->dbpdrga); 171*1251e490SNobuhiro Iwamatsu dbpdrgd_check(dbsc3_0); 172*1251e490SNobuhiro Iwamatsu 173*1251e490SNobuhiro Iwamatsu writel(0x00000000, &dbsc3_0->dbbs0cnt1); 174*1251e490SNobuhiro Iwamatsu writel(0x01004C20, &dbsc3_0->dbcalcnf); 175*1251e490SNobuhiro Iwamatsu writel(0x014000AA, &dbsc3_0->dbcaltr); 176*1251e490SNobuhiro Iwamatsu writel(0x00000140, &dbsc3_0->dbrfcnf0); 177*1251e490SNobuhiro Iwamatsu writel(0x00081860, &dbsc3_0->dbrfcnf1); 178*1251e490SNobuhiro Iwamatsu writel(0x00010000, &dbsc3_0->dbrfcnf2); 179*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbrfen); 180*1251e490SNobuhiro Iwamatsu writel(0x00000001, &dbsc3_0->dbacen); 181*1251e490SNobuhiro Iwamatsu } 182*1251e490SNobuhiro Iwamatsu #else 183*1251e490SNobuhiro Iwamatsu #define bsc_init() do {} while (0) 184*1251e490SNobuhiro Iwamatsu #endif /* CONFIG_NORFLASH */ 185*1251e490SNobuhiro Iwamatsu 186*1251e490SNobuhiro Iwamatsu void s_init(void) 187*1251e490SNobuhiro Iwamatsu { 188*1251e490SNobuhiro Iwamatsu struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE; 189*1251e490SNobuhiro Iwamatsu struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE; 190*1251e490SNobuhiro Iwamatsu 191*1251e490SNobuhiro Iwamatsu /* Watchdog init */ 192*1251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &rwdt->rwtcsra); 193*1251e490SNobuhiro Iwamatsu writel(0xA5A5A500, &swdt->swtcsra); 194*1251e490SNobuhiro Iwamatsu 195*1251e490SNobuhiro Iwamatsu /* QoS */ 196*1251e490SNobuhiro Iwamatsu qos_init(); 197*1251e490SNobuhiro Iwamatsu 198*1251e490SNobuhiro Iwamatsu /* BSC */ 199*1251e490SNobuhiro Iwamatsu bsc_init(); 200*1251e490SNobuhiro Iwamatsu } 201*1251e490SNobuhiro Iwamatsu 202*1251e490SNobuhiro Iwamatsu #define MSTPSR1 0xE6150038 203*1251e490SNobuhiro Iwamatsu #define SMSTPCR1 0xE6150134 204*1251e490SNobuhiro Iwamatsu #define TMU0_MSTP125 (1 << 25) 205*1251e490SNobuhiro Iwamatsu 206*1251e490SNobuhiro Iwamatsu #define MSTPSR7 0xE61501C4 207*1251e490SNobuhiro Iwamatsu #define SMSTPCR7 0xE615014C 208*1251e490SNobuhiro Iwamatsu #define SCIF0_MSTP721 (1 << 21) 209*1251e490SNobuhiro Iwamatsu 210*1251e490SNobuhiro Iwamatsu #define PMMR 0xE6060000 211*1251e490SNobuhiro Iwamatsu #define GPSR4 0xE6060014 212*1251e490SNobuhiro Iwamatsu #define IPSR14 0xE6060058 213*1251e490SNobuhiro Iwamatsu 214*1251e490SNobuhiro Iwamatsu #define set_guard_reg(addr, mask, value) \ 215*1251e490SNobuhiro Iwamatsu { \ 216*1251e490SNobuhiro Iwamatsu u32 val; \ 217*1251e490SNobuhiro Iwamatsu val = (readl(addr) & ~(mask)) | (value); \ 218*1251e490SNobuhiro Iwamatsu writel(~val, PMMR); \ 219*1251e490SNobuhiro Iwamatsu writel(val, addr); \ 220*1251e490SNobuhiro Iwamatsu } 221*1251e490SNobuhiro Iwamatsu 222*1251e490SNobuhiro Iwamatsu #define mstp_setbits(type, addr, saddr, set) \ 223*1251e490SNobuhiro Iwamatsu out_##type((saddr), in_##type(addr) | (set)) 224*1251e490SNobuhiro Iwamatsu #define mstp_clrbits(type, addr, saddr, clear) \ 225*1251e490SNobuhiro Iwamatsu out_##type((saddr), in_##type(addr) & ~(clear)) 226*1251e490SNobuhiro Iwamatsu #define mstp_setbits_le32(addr, saddr, set) \ 227*1251e490SNobuhiro Iwamatsu mstp_setbits(le32, addr, saddr, set) 228*1251e490SNobuhiro Iwamatsu #define mstp_clrbits_le32(addr, saddr, clear) \ 229*1251e490SNobuhiro Iwamatsu mstp_clrbits(le32, addr, saddr, clear) 230*1251e490SNobuhiro Iwamatsu 231*1251e490SNobuhiro Iwamatsu int board_early_init_f(void) 232*1251e490SNobuhiro Iwamatsu { 233*1251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 234*1251e490SNobuhiro Iwamatsu 235*1251e490SNobuhiro Iwamatsu #if defined(CONFIG_NORFLASH) 236*1251e490SNobuhiro Iwamatsu /* SCIF0 */ 237*1251e490SNobuhiro Iwamatsu set_guard_reg(GPSR4, 0x34000000, 0x00000000); 238*1251e490SNobuhiro Iwamatsu set_guard_reg(IPSR14, 0x00000FC7, 0x00000481); 239*1251e490SNobuhiro Iwamatsu set_guard_reg(GPSR4, 0x00000000, 0x34000000); 240*1251e490SNobuhiro Iwamatsu #endif 241*1251e490SNobuhiro Iwamatsu 242*1251e490SNobuhiro Iwamatsu mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 243*1251e490SNobuhiro Iwamatsu 244*1251e490SNobuhiro Iwamatsu return 0; 245*1251e490SNobuhiro Iwamatsu } 246*1251e490SNobuhiro Iwamatsu 247*1251e490SNobuhiro Iwamatsu int board_init(void) 248*1251e490SNobuhiro Iwamatsu { 249*1251e490SNobuhiro Iwamatsu /* adress of boot parameters */ 250*1251e490SNobuhiro Iwamatsu gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100; 251*1251e490SNobuhiro Iwamatsu 252*1251e490SNobuhiro Iwamatsu /* Init PFC controller */ 253*1251e490SNobuhiro Iwamatsu r8a7791_pinmux_init(); 254*1251e490SNobuhiro Iwamatsu 255*1251e490SNobuhiro Iwamatsu return 0; 256*1251e490SNobuhiro Iwamatsu } 257*1251e490SNobuhiro Iwamatsu 258*1251e490SNobuhiro Iwamatsu int dram_init(void) 259*1251e490SNobuhiro Iwamatsu { 260*1251e490SNobuhiro Iwamatsu gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 261*1251e490SNobuhiro Iwamatsu gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 262*1251e490SNobuhiro Iwamatsu 263*1251e490SNobuhiro Iwamatsu return 0; 264*1251e490SNobuhiro Iwamatsu } 265*1251e490SNobuhiro Iwamatsu 266*1251e490SNobuhiro Iwamatsu const struct rmobile_sysinfo sysinfo = { 267*1251e490SNobuhiro Iwamatsu CONFIG_RMOBILE_BOARD_STRING 268*1251e490SNobuhiro Iwamatsu }; 269*1251e490SNobuhiro Iwamatsu 270*1251e490SNobuhiro Iwamatsu void dram_init_banksize(void) 271*1251e490SNobuhiro Iwamatsu { 272*1251e490SNobuhiro Iwamatsu gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE; 273*1251e490SNobuhiro Iwamatsu gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE; 274*1251e490SNobuhiro Iwamatsu } 275*1251e490SNobuhiro Iwamatsu 276*1251e490SNobuhiro Iwamatsu int board_late_init(void) 277*1251e490SNobuhiro Iwamatsu { 278*1251e490SNobuhiro Iwamatsu return 0; 279*1251e490SNobuhiro Iwamatsu } 280*1251e490SNobuhiro Iwamatsu 281*1251e490SNobuhiro Iwamatsu void reset_cpu(ulong addr) 282*1251e490SNobuhiro Iwamatsu { 283*1251e490SNobuhiro Iwamatsu } 284